# US 11,908,730 B2 · Vertical semiconductor device and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,730 B2 - Document ID: US11908730B2 - Status: Granted - Kind: B2 - Application number: 17/356,226 - Filed: 2021-06-23 - Published: 2021-10-14 - Granted: 2024-02-20 - Earliest claimed: 2019-07-26 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jong-Hoon Kim - Web page: https://patentgrep.com/patent/US11908730B2 ## CPC - H10B 43/40: characterised by the peripheral circuit region - H10W 20/081: {by forming openings in the dielectric parts} - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10B 43/10: characterised by the top-view layout - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for fabricating a semiconductor device includes preparing a substrate including a first region and a second region, forming a lower alternating stack on the substrate; etching the lower alternating stack to form a lower opening in the second region, forming an upper alternating stack on the lower opening and the lower alternating stack to form recess portion caused by filling the lower opening in the second region, forming a mask layer on the upper alternating stack using the recess portion as an alignment key, and etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region. ## Claims ### Claim 1 A vertical semiconductor device comprising: a substrate including a memory cell region and an alignment key region; a memory cell stack in which dielectric layers and gate electrodes are alternately stacked in the memory cell region; a dummy stack formed in the alignment key region; a lower channel structure that penetrates a lower portion of the memory cell stack; an upper channel structure that penetrates an upper portion of the memory cell stack and is located on the lower channel structure; a lower stepped alignment key having a trench shape and disposed in a lower portion of the dummy stack; and an upper stepped alignment key disposed in an upper portion of the dummy stack and caused by the lower stepped alignment key. ### Claim 2 (depends on 1) The vertical semiconductor device of claim 1, wherein the lower stepped alignment key includes a pattern of openings. ### Claim 3 (depends on 2) The vertical semiconductor device of claim 2, wherein the openings comprise about 10% of a surface area of the pattern. ### Claim 4 (depends on 2) The vertical semiconductor device of claim 2, wherein cross sections of the openings have square shapes. ### Claim 5 (depends on 2) The vertical semiconductor device of claim 2, wherein the pattern includes an array of openings each spaced apart from one another in two dimensions. ### Claim 6 (depends on 1) The vertical semiconductor device of claim 1, wherein the dummy stack comprises alternating stack in which different dielectric materials are alternately stacked. ### Claim 7 (depends on 1) The vertical semiconductor device of claim 1, wherein the upper stepped alignment key includes a flat portion and a recess portion lower in height than the flat portion, and the recess portion is used as an alignment key for aligning the lower and upper channel structures. ### Claim 8 (depends on 1) The vertical semiconductor device of claim 1, wherein cross sections of the lower stepped alignment key have square shapes. ### Claim 9 (depends on 1) The vertical semiconductor device of claim 1, wherein the lower stepped alignment key comprising: a lower alternating dummy stack; and a plurality of openings passing through the lower alternating dummy stack. ### Claim 10 (depends on 9) The vertical semiconductor device of claim 9, wherein the upper stepped alignment key comprising an upper alternating stack, wherein the upper alternating stack includes a recess portion filling the openings of the lower alternating dummy stack; and a flat portion extending from the recess portion. ### Claim 11 A semiconductor device comprising: a substrate including an alignment key region; a dummy stack formed in the alignment key region; a lower stepped alignment key having a trench shape and disposed in a lower portion of the dummy stack; and an upper stepped alignment key disposed in an upper portion of the dummy stack and caused by the lower stepped alignment key. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the lower stepped alignment key includes a pattern of openings. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the openings comprise about 10% of a surface area of the pattern. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein cross sections of the openings have square shapes. ### Claim 15 (depends on 12) The semiconductor device of claim 12, wherein the pattern includes an array of openings each spaced apart from one another in two dimensions. ### Claim 16 (depends on 11) The semiconductor device of claim 11, wherein the dummy stack comprises alternating stack in which different dielectric materials are alternately stacked. ### Claim 17 (depends on 11) The semiconductor device of claim 11, wherein the upper stepped alignment key includes a flat portion and a recess portion lower in height than the flat portion, and the recess portion is used as an alignment key. ### Claim 18 (depends on 11) The semiconductor device of claim 11, wherein the lower stepped alignment key are a line and space-shaped pattern, and the line shape of the line and space-shaped pattern includes a closed portion, and the space shape of the line and space-shaped pattern is divided into a plurality of sub-closed portions and a plurality of opened portions. ### Claim 19 (depends on 11) The semiconductor device of claim 11, wherein the lower stepped alignment key comprising: a lower alternating dummy stack; and a plurality of openings passing through the lower alternating dummy stack. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein the upper stepped alignment key comprising an upper alternating stack, wherein the upper alternating stack includes a recess portion filling the openings of the lower alternating dummy stack; and a flat portion extending from the recess portion.