# US 11,908,729 B2 · Selective etches for reducing cone formation in shallow trench isolations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,729 B2 - Document ID: US11908729B2 - Status: Granted - Kind: B2 - Application number: 17/478,306 - Filed: 2021-09-17 - Published: 2022-01-06 - Granted: 2024-02-20 - Earliest claimed: 2017-12-22 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Karen Hildegard Ralston Kirmse; Jonathan Philip Davis - Web page: https://patentgrep.com/patent/US11908729B2 ## CPC - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10P 50/242: {of Group IV materials} - H10P 50/283: {by chemical means} - H10P 50/691: {for Group IV materials or Group III-V materials} - H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation. ## Claims ### Claim 1 An integrated circuit, comprising: a semiconductor substrate having a surface; a first isolation structure along the surface, the first isolation structure having a first feature dimension and a first sidewall slope; a second isolation structure along the surface, the second isolation structure having a second feature dimension greater than the first feature dimension, the second isolation structure having a second sidewall slope within a 15 degrees of deviation from the first sidewall slope; a transistor structure laterally isolated by the first isolation structure; and a circuit component integrating the second isolation structure; wherein the first feature dimension includes a first inter-trench spacing; and the second feature dimension includes a second inter-trench spacing at least 2 times greater than the first inter-trench spacing. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the circuit component includes at least one of a resistor, an inductor, or a capacitor. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the circuit component includes a gate structure of a lateral diffused MOS transistor. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the transistor structure includes at least one of a MOS transistor or a bipolar junction transistor. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the transistor structure includes a memory cell transistor. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the second sidewall slope is greater than 85 degrees. ### Claim 7 An integrated circuit, comprising: a semiconductor substrate having a surface; a first isolation structure along the surface, the first isolation structure having a first feature dimension and a first sidewall slope; a second isolation structure along the surface, the second isolation structure having a second feature dimension greater than the first feature dimension, the second isolation structure having a second sidewall slope within a 15 degrees of deviation from the first sidewall slope; a transistor structure laterally isolated by the first isolation structure; and a circuit component integrating the second isolation structure; wherein: the semiconductor substrate is divided into a first region and a second region; the first region has a higher component density than the second region; the first isolation structure is positioned within the first region; and the second isolation structure is positioned within the second region. ### Claim 8 An integrated circuit, comprising: a semiconductor substrate having a surface; a first isolation structure along the surface, the first isolation structure having a first feature dimension and a first sidewall slope; a second isolation structure along the surface, the second isolation structure having a second feature dimension greater than the first feature dimension, the second isolation structure having a second sidewall slope within a 15 degrees of deviation from the first sidewall slope; wherein: the first feature dimension includes a first trench width; and the second feature dimension includes a second trench width at least 2 times greater than the first trench width. ### Claim 9 (depends on 7) The integrated circuit of claim 7, wherein the circuit component includes at least one of a resistor, an inductor, or a capacitor. ### Claim 10 (depends on 7) The integrated circuit of claim 7, wherein the circuit component includes a gate structure of a lateral diffused MOS transistor. ### Claim 11 (depends on 7) The integrated circuit of claim 7, wherein the transistor structure includes at least one of a MOS transistor or a bipolar junction transistor. ### Claim 12 (depends on 7) The integrated circuit of claim 7, wherein the transistor structure includes a memory cell transistor. ### Claim 13 (depends on 7) The integrated circuit of claim 7, wherein the second sidewall slope is greater than 85 degrees. ### Claim 14 (depends on 8) The integrated circuit of claim 8, wherein the circuit component includes at least one of a resistor, an inductor, or a capacitor. ### Claim 15 (depends on 8) The integrated circuit of claim 8, wherein the circuit component includes a gate structure of a lateral diffused MOS transistor. ### Claim 16 (depends on 8) The integrated circuit of claim 8, wherein the transistor structure includes at least one of a MOS transistor or a bipolar junction transistor. ### Claim 17 (depends on 8) The integrated circuit of claim 8, wherein the transistor structure includes a memory cell transistor. ### Claim 18 (depends on 8) The integrated circuit of claim 8, wherein the second sidewall slope is greater than 85 degrees.