# US 11,908,705 B2 · Interconnect singulation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,705 B2 - Document ID: US11908705B2 - Status: Granted - Kind: B2 - Application number: 17/504,148 - Filed: 2021-10-18 - Published: 2023-04-20 - Granted: 2024-02-20 - Earliest claimed: 2021-10-18 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Chih-Chien Ho - Web page: https://patentgrep.com/patent/US11908705B2 ## CPC - H10W 70/048: {Mechanical treatments, e.g. punching, cutting, deforming or cold welding} - H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes} - H10W 74/014: {using batch processing} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for aligning interconnects that includes trimming and forming a frame of strips of interconnects. The frame of strips of interconnects includes interdigitated pins. The method also includes removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects. The method includes aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects. A strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects. The method further includes singulating the aligned array of strips of interconnects. ## Claims ### Claim 1 A method for aligning interconnects comprising: trimming and forming a frame of strips of interconnects, wherein the frame of strips of interconnects comprises interdigitated pins; removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects; aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects, wherein a strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects; and singulating the aligned array of strips of interconnects to provide interconnects for dies of integrated circuit (IC) chips. ### Claim 2 (depends on 1) The method of claim 1, wherein cutting the siderails from the strips of interconnects further comprises: cutting a first edge and a second edge of the strips of interconnects in the frame of strips of interconnects. ### Claim 3 (depends on 1) The method of claim 1, wherein the siderails attached to the frame of strips of interconnects has seats for the strips of interconnects, and the seats of the strips of interconnects have a same shape. ### Claim 4 (depends on 1) The method of claim 1, wherein the pins of the first set of strips of interconnects in the array of strips of interconnects are interleaved with the pins of the second set of strips of interconnects in the array of strips of interconnects. ### Claim 5 (depends on 1) The method of claim 1, wherein the strips of interconnects in the frames of interconnects comprises die pads for dies of the integrated circuit (IC) chips. ### Claim 6 (depends on 1) The method of claim 1, wherein the interconnects for dies of the IC chips are dual in-line package interconnects. ### Claim 7 A method for aligning interconnects comprising: trimming and forming a frame of strips of interconnects, wherein the frame of strips of interconnects comprises interdigitated pins; removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects, including cutting a first edge and a second edge of the strips of interconnects in the frame of strips of interconnects; aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects, wherein a strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects, moving a given strip of interconnects of the first set of strips of interconnects from an initial position along a first axis; measuring an offset of pins on the given strip of interconnects of the first set of strips of interconnects relative to pins of the second set of strips of interconnects; moving the first set of strips of interconnects along a second axis by the measured offset, wherein the second axis is perpendicular to the first axis; returning the first set of strips of interconnects to the initial position; and singulating the aligned array of strips of interconnects to provide interconnects for dies of integrated circuit (IC) chips. ### Claim 8 (depends on 7) The method of claim 7, wherein aligning a first set of strips of interconnects further comprises: ascending the given strip of interconnects along a third axis from a sawing chuck table to the initial position, wherein the third axis is perpendicular to the first axis and the second axis. ### Claim 9 (depends on 8) The method of claim 8, wherein aligning a first set of strips of interconnects further comprises: descending the given strip of interconnects along the third axis from the initial position to the sawing chuck table in response to the returning. ### Claim 10 (depends on 7) The method of claim 7, wherein the measuring comprises: capturing an image of the given strip of interconnects; comparing the image of the given strip of interconnects to an image of another strip of interconnects; and determining a distance between pins on the given strip of interconnects with pins of the other strip of interconnects, wherein the distance is the offset of the pins of the given strip of interconnects. ### Claim 11 (depends on 10) The method of claim 10, wherein the pins of the first set of strips of interconnects are aligned within 25 micrometers of the pins of the second set of strips of interconnects in the aligned array of strips of interconnects. ### Claim 12 A method for aligning interconnects comprising: trimming and forming a frame of strips of interconnects, wherein the frame of strips of interconnects comprises interdigitated pins; removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects; aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects, wherein a strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects; flipping the first set of strips of interconnects of the array of strips of interconnects and the second set of strips of interconnects of the array of strips of interconnects; resting the flipped first set of strips of interconnects of the array of strips of interconnects and the flipped second set of strips of interconnects of the array of strips of interconnects on a sawing chuck table; and singulating the aligned array of strips of interconnects to provide interconnects for dies of integrated circuit (IC) chips. ### Claim 13 (depends on 12) The method of claim 12, wherein the sawing chuck table comprises first pillars and second pillars for the array of strips of interconnects, wherein each first pillar of the first pillars is spaced apart from a corresponding second pillar of the second pillars. ### Claim 14 A method for aligning interconnects comprising: trimming and forming a frame of strips of interconnects, wherein the frame of strips of interconnects comprises interdigitated pins; removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects; after the trimming and forming the frame of strips of interconnects and after removing the siderails, aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects, wherein a strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects; and singulating the aligned array of strips of interconnects to provide interconnects for dies of integrated circuit (IC) chips. ### Claim 15 (depends on 1) The method of claim 1, wherein cutting the siderails from the strips of interconnects further comprises: cutting a first edge and a second edge of the strips of interconnects in the frame of strips of interconnects. ### Claim 16 (depends on 15) The method of claim 15, wherein singulating the array of aligned strips of interconnects further comprises: making parallel crosscuts in the aligned array of strips of interconnects. ### Claim 17 (depends on 15) The method of claim 15, wherein aligning a first set of strips of interconnects in the array of strips of interconnects further comprises: moving a given strip of interconnects of the first set of strips of interconnects from an initial position along a first axis; measuring an offset of pins on the given strip of interconnects of the first set of strips of interconnects relative to pins of the second set of strips of interconnects; moving the first set of strips of interconnects along a second axis by the measured offset, wherein the second axis is perpendicular to the first axis; and returning the first set of strips of interconnects to the initial position. ### Claim 18 (depends on 17) The method of claim 17, wherein aligning a first set of strips of interconnects further comprises: ascending the given strip of interconnects along a third axis from a sawing chuck table to the initial position, wherein the third axis is perpendicular to the first axis and the second axis. ### Claim 19 A method for aligning interconnects comprising: trimming and forming a frame of strips of interconnects, wherein the frame of strips of interconnects comprises interdigitated pins; removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects, including cutting a first edge and a second edge of the strips of interconnects in the frame of strips of interconnects; aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects, wherein a strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects; and making parallel crosscuts in the aligned array of strips of interconnects to singulate the aligned array of strips of interconnects to provide interconnects for dies of integrated circuit (IC) chips. ### Claim 20 A method for aligning interconnects comprising: trimming and forming a frame of strips of interconnects, wherein the frame of strips of interconnects comprises interdigitated pins, wherein the strip of interconnects of the first set of strips of interconnects have a first distance between an edge of a respective strip of interconnects of the first strip of interconnects and a pin nearest to the edge of the respective strip of interconnects of the first strip of interconnects, and the strips of interconnects of the second set of strips of interconnects have a second distance between an edge of a respective strip of interconnects of the second set of strips of interconnects and a pin nearest to the edge of the respective strip of interconnects of the second set of strips of interconnects, the first distance being different than the second distance, wherein the pins of the first set of strips of interconnects in the array of strips of interconnects are interleaved with the pins of the second set of strips of interconnects in the array of strips of interconnects; removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects; aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects, wherein a strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects; and singulating the aligned array of strips of interconnects to provide interconnects for dies of integrated circuit (IC) chips.