# US 11,908,695 B2 · Replacement gate methods that include treating spacers to widen gate

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- Number: US 11,908,695 B2
- Document ID: US11908695B2
- Status: Granted
- Kind: B2
- Application number: 17/377,839
- Filed: 2021-07-16
- Published: 2021-11-04
- Granted: 2024-02-20
- Earliest claimed: 2018-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shu-Han Chen; Tsung-Ju Chen; Ta-Hsiang Kung; Xiong-Fei Yu; Chi On Chui
- Web page: https://patentgrep.com/patent/US11908695B2

## CPC

- H10D 64/01334: {by defining the insulator using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/675: {Gate sidewall spacers}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6532: {by exposure to a plasma}
- H10P 50/283: {by chemical means}
- H10P 95/064: {the removal being chemical etching}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

## Claims

### Claim 1

A device, comprising:
a plurality of source/drain regions formed in a substrate;
a gate structure over the substrate between the plurality of source/drain regions, wherein the gate structure comprises one or more gate dielectric layers and one or more gate electrode layers; and
a plurality of spacers surrounding the gate structure, wherein a first spacer of the plurality of spacers contacts the one or more gate dielectric layers, wherein the first spacer has a first thickness at a first location and a second thickness at a second location, wherein the first location is farthest from the substrate and the second location is between the first location and the substrate, and wherein a first sidewall of the first spacer that contacts the one or more gate dielectric layers extends at an angle between the first location and the second location, the angle is with respect to a direction that is perpendicular to a major surface of the substrate, and the angle is greater than or equal to 3 degrees.

### Claim 2 (depends on 1)

The device of claim 1, wherein a sidewall of the one or more gate dielectric layers that contacts the first spacer extends at a same angle as the first sidewall of the first spacer.

### Claim 3 (depends on 1)

The device of claim 1, wherein a second sidewall of the first spacer extends in the direction that is perpendicular to the major surface of the substrate, the second sidewall being opposite to the first sidewall.

### Claim 4 (depends on 1)

The device of claim 1, wherein a thickness of the first spacer varies according to height of the first spacer between the first location and the second location, wherein the height is in the direction that is perpendicular to the major surface of the substrate.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first spacer comprises SIONC.

### Claim 6 (depends on 1)

The device of claim 1, wherein the first spacer comprises Si1-x-y-zOxNyCz, where x is about 45%±15%, y is about 15%±15% and z is 10%±10%.

### Claim 7 (depends on 1)

The device of claim 1, wherein the plurality of spacers comprises a second spacer, wherein the first spacer is interposed between the second spacer and the one or more gate dielectric layers, wherein the second spacer directly contacts the one or more gate dielectric layers.

### Claim 8 (depends on 1)

The device of claim 1, further comprising a dielectric layer, wherein the dielectric layer is interposed between the plurality of spacers and the substrate.

### Claim 9

A device, comprising:
a first source/drain region and a second source/drain region formed in a substrate;
a gate structure over the substrate between the first source/drain region and the second source/drain region, wherein the gate structure comprises a gate dielectric layer and one or more conductive layers over the gate dielectric layer;
a first spacer on a sidewall of the gate structure; and
a second spacer on a first sidewall of the first spacer opposite the gate structure, wherein a second sidewall of the first spacer tapers at an angle greater than or equal to 3 degrees relative to a line perpendicular to a surface of the substrate in a cross-sectional view.

### Claim 10 (depends on 9)

The device of claim 9, wherein a width of the gate structure at an upper surface in the cross-sectional view is 0% to 30% greater than a width of the gate structure at a lower surface in the cross-sectional view.

### Claim 11 (depends on 9)

The device of claim 9, wherein a thickness of the first spacer decreases as the first spacer extends away from the substrate.

### Claim 12 (depends on 9)

The device of claim 9, further comprising a dielectric layer interposed between the first spacer and the substrate, wherein the dielectric layer is interposed between the second spacer and the substrate.

### Claim 13 (depends on 12)

The device of claim 12, wherein the gate structure extends along a sidewall of the dielectric layer.

### Claim 14 (depends on 9)

The device of claim 9, wherein the first spacer comprises SiONC.

### Claim 15 (depends on 9)

The device of claim 9, wherein a width of the gate structure at an upper surface in the cross-sectional view is greater than a width of the gate structure at a lower surface in the cross-sectional view by 0 nm to 6.0 nm.

### Claim 16

A device, comprising:
a first source/drain region and a second source/drain region formed in a substrate;
a gate structure over the substrate between the first source/drain region and the second source/drain region, wherein the gate structure comprises a gate dielectric layer and one or more conductive layers over the gate dielectric layer;
a first spacer on a sidewall of the gate structure, a first sidewall of the first spacer facing the gate structure and a second sidewall of the first spacer facing away from the gate structure, the first sidewall of the first spacer having a first slope; and
a second spacer on the second sidewall of the first spacer opposite the gate structure, wherein a sidewall of the second spacer facing the first spacer having a second slope different than the first slope.

### Claim 17 (depends on 16)

The device of claim 16, wherein the first spacer comprises SiONC, wherein the second spacer comprises silicon nitride, SiCN, or a combination thereof.

### Claim 18 (depends on 16)

The device of claim 16, wherein a thickness of the first spacer decreases as the first spacer extends away from the substrate, wherein a thickness of the second spacer decreases as the second spacer extends away from the substrate.

### Claim 19 (depends on 18)

The device of claim 18, further comprising a dielectric layer extending from the gate structure to the first source/drain region, wherein the first spacer and the second spacer contacts an upper surface of the dielectric layer.

### Claim 20 (depends on 16)

The device of claim 16, wherein the gate structure contacts the second spacer.