# US 11,908,693 B2 · Method for preparing semiconductor device structure with lining layer

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- Number: US 11,908,693 B2
- Document ID: US11908693B2
- Status: Granted
- Kind: B2
- Application number: 17/669,556
- Filed: 2022-02-11
- Published: 2023-08-17
- Granted: 2024-02-20
- Earliest claimed: 2022-02-11
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Ping Hsu
- Web page: https://patentgrep.com/patent/US11908693B2

## CPC

- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/076: {in via holes or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first mask patterns over the target layer. The method also includes forming a lining layer conformally covering the first mask patterns and the target layer. A first opening is formed over the lining layer and between the first mask patterns. The method further includes filling the first opening with a second mask pattern, and performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer.

## Claims

### Claim 1

A method for preparing a semiconductor device structure, comprising:
forming a target layer over a semiconductor substrate;
forming a plurality of first mask patterns over the target layer;
forming a lining layer conformally covering the first mask patterns and the target layer, wherein a first opening is formed over the lining layer and between the first mask patterns;
filling the first opening with a plurality of second mask patterns by the steps of:
forming a second mask layer on the lining layer, wherein the second mask layer has a first portion filled in the first opening and a second portion formed over a top surface of the lining layer; and
removing the second portion of the second mask layer, wherein the first portion of the second mask layer is remained in the first opening to form each of the second mask patterns between the first mask patterns, such that the second mask patterns are alternating with the first mask patterns, wherein a flat top surface of the second mask pattern is coplanar with a flat top surface of the lining layer; and
performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer, wherein each of the second openings is formed between the first mask pattern and the second mask pattern, wherein a width of each of the second openings is smaller than a width of each of the first openings, wherein the etching process comprises the steps of:
during a first stage of the etching process, a top portion of the lining layer above top surfaces of the first mask patterns is etched to expose the first mask patterns, wherein an etching rate of the lining layer is higher than an etching rate of the second mask patterns, wherein the top surfaces of the first mask patterns are coplanar with the flat top surface of the lining layer after the first stage of the etching process;
during a second stage of the etching process, removing portions of the lining layers between the first mask patterns and second mask pattern are etched to be removed to form a plurality of third openings so as to expose a top surface of the target layer, wherein the etching rate of the lining layer is higher than an etching rate of the first mask patterns; and
during a third stage of the etching process, deepening the third openings in the target layer to form the second openings respectively, wherein a bottom of each of the third openings is above a bottom of the target layer, such that a width of the target layer at the second opening is reduced and is smaller than a width of the target layer at the first mask pattern;
wherein after the third stage of the etching process, the target layer is etched to form a base portion coving the semiconductor substrate and a plurality of protruding portions integrally, spacedly, and upwardly extended from the base portion, wherein each of the third openings is defined between every two of the protruding portions and the base portion, such that the third openings are alternating with the protruding portions and located above the base portion.

### Claim 2 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein the first mask patterns are in direct contact with the target layer, and the second mask pattern is separated from the target layer by the lining layer, wherein the target layer has a uniform thickness and the top surface thereof is a flat top surface, wherein the first mask patterns are spacedly and upwardly extended from the flat top surface of the target layer when the first mask patterns are covered by the lining layer, wherein at the third stage of the etching process, the width of the target layer is reduced by deepening the third opening to form the base portion in order to cover on the semiconductor substrate.

### Claim 3 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein the second mask patterns are separated from the first mask patterns by the lining layer, wherein the second mask pattern is positioned at a middle of the first opening, such that intervals between the first mask pattern and the second mask pattern are the same.

### Claim 4 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein the lining layer includes an organic polymer material, wherein a pitch between every two of the protruding portions of the target layer is equal to a pitch between the second mask patterns and the first mask pattern, and is less than a pitch between the first mask patterns.

### Claim 5 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein the flat top surface of the second mask pattern in the first opening is higher than the top surfaces of the first mask patterns, wherein two of the second openings and one of the second mask patterns are located between two of the first mask patterns in an adjacent position.

### Claim 6 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein the flat top surface of the second mask pattern is substantially coplanar with the flat top surface of the lining layer before the etching process is performed, wherein the top flat surface of the second mask pattern is higher than the flat top surface of the lining layer after the second portion of the second mask layer is removed.

### Claim 7 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, further comprising a step of removing the lining layer, the first mask pattern, and the second mask pattern after the etching process, wherein the etching process includes a dry etching process.

### Claim 8 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein during the first stage of the etching process, the second mask pattern is an etching mask preventing underlying portions of the lining layer from being etched, while portions of the lining layer above the lining layer are etched to expose the first mask patterns.

### Claim 9 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein a fourth opening between two adjacent first mask patterns of the first mask patterns has a first width, and each of the second openings in the target layer has a second width less than the first width.

### Claim 10 (depends on 1)

The method for preparing a semiconductor device structure of claim 1, wherein a remaining portion of the lining layer is sandwiched between the second mask pattern and the target layer after the second stage of the etching process is performed.

### Claim 11 (depends on 10)

The method for preparing a semiconductor device structure of claim 10, wherein the remaining portion of the lining layer, the first mask patterns, and the second mask pattern are removed after the second openings are formed in the target layer.