# US 11,908,692 B2 · Method for fabricating a chip package

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- Number: US 11,908,692 B2
- Document ID: US11908692B2
- Status: Granted
- Kind: B2
- Application number: 17/458,557
- Filed: 2021-08-27
- Published: 2021-12-16
- Granted: 2024-02-20
- Earliest claimed: 2017-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jie Chen; Hsien-Wei Chen; Tzuan-Horng Liu; Ying-Ju Chen
- Web page: https://patentgrep.com/patent/US11908692B2

## CPC

- H10P 76/2041: {Photolithographic processes}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 70/277: {the processing being a planarisation of conductive layers}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7412: {the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/655: Fan-out layouts
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/00: Package configurations
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/798: {between a chip and a stacked discrete passive device}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

## Claims

### Claim 1

A method, comprising:
performing a first exposure process using a first mask to transfer a first layout pattern of the first mask onto a photoresist layer;
performing a first development process to form a first wiring opening with the first layout pattern in the photoresist layer;
after performing the first development process, performing a second exposure process using a second mask to transfer a second layout pattern of the second mask onto the photoresist layer, wherein the second layout pattern transferred onto the photoresist layer is substantially aligned with and overlaps an overlay region of the first wiring opening;
performing a second development process to form a second wiring opening with the second layout pattern in the photoresist layer, wherein the first wiring opening and the second wiring opening are communicated at the overlay region; and
after performing the second development process, forming a conductive wiring in the first wiring opening and the second wiring opening.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the overlay region of the first wiring opening is covered by the second mask when performing the second exposure process.

### Claim 3 (depends on 1)

The method as claimed in claim 1 further comprising:
removing the photoresist layer after forming the conductive wiring.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein a first width of the first wiring opening formed within the overlay region is greater than a second width of the first wiring opening formed outside the overlay region.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein the conductive wiring comprises a first conductive segment formed in the first wiring opening and a second conductive segment formed in the second wiring opening.

### Claim 6 (depends on 5)

The method as claimed in claim 5, wherein an overlay offset occurs between the first conductive segment and the second conductive segment.

### Claim 7

A method, comprising:
performing a first exposure process using a first mask to transfer a first alignment pattern and a first layout pattern onto a photoresist layer;
performing a first development process to form a first alignment opening and a first wiring opening in the photoresist layer;
performing a second exposure process using a second mask to transfer a second alignment pattern and a second layout pattern onto the photoresist layer, wherein the second layout pattern transferred onto the photoresist layer is substantially aligned with and overlaps an overlay region of the first wiring opening, and the second alignment pattern of the second mask is substantially aligned with the first alignment opening formed in the photoresist layer when performing the second exposure process;
performing a second development process to form a second alignment opening and a second wiring opening in the photoresist layer, wherein the first wiring opening and the second wiring opening are communicated at the overlay region;
forming alignment marks in the first alignment opening and the second alignment opening; and
forming a conductive wiring in the first wiring opening and the second wiring opening.

### Claim 8 (depends on 7)

The method as claimed in claim 7 further comprising:
removing the photoresist layer after forming the conductive wiring.

### Claim 9 (depends on 7)

The method as claimed in claim 7, wherein the second alignment opening spaced apart from the first alignment opening is formed in the photoresist layer after performing the second development process.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein the alignment marks comprise a first alignment mark formed in the first alignment opening and a second alignment mark formed in the second alignment opening.

### Claim 11 (depends on 10)

The method as claimed in claim 10, wherein the first alignment mark has an alignment notch, and the second alignment mark extends into the alignment notch.

### Claim 12 (depends on 10)

The method as claimed in claim 10, wherein the second alignment mark has an alignment notch, and the first alignment mark extends into the alignment notch.

### Claim 13 (depends on 7)

The method as claimed in claim 7, wherein the first layout pattern of the first mask comprises a first light-shielding pattern having a first light-transmissive region corresponding to the first wiring opening, and the second layout pattern of the second mask comprises a second light-shielding pattern having a second light-transmissive region corresponding to the second wiring opening.

### Claim 14 (depends on 7)

The method as claimed in claim 7, wherein
the first mask comprises a first overlay area corresponding to the overlay region,
the second mask comprises a second overlay area corresponding to the overlay region,
the first alignment pattern is distributed in the first overlay area of the first mask,
the second alignment pattern is distributed in the second overlay area of the second mask, and
when performing the second exposure process, the second overlay area of the second mask covers the first alignment opening formed in the photoresist layer.

### Claim 15

A method for fabricating a chip package, comprising:
laterally encapsulating an integrated circuit component with an insulating encapsulation;
forming a conductive layer over the integrated circuit component and the insulating encapsulation;
patterning the photoresist layer, comprising:
performing a first exposure process using a first mask to transfer a first alignment pattern and a first layout pattern onto a photoresist layer;
performing a first development process to form a first alignment opening and a first wiring opening in the photoresist layer;
performing a second exposure process using a second mask to transfer a second alignment pattern and a second layout pattern onto the photoresist layer, wherein the second layout pattern transferred onto the photoresist layer is substantially aligned with and overlaps an overlay region of the first wiring opening, and the second alignment pattern of the second mask is substantially aligned with the first alignment opening formed in the photoresist layer when performing the second exposure process;
performing a second development process to form a second alignment opening and a second wiring opening in the photoresist layer, wherein the first wiring opening and the second wiring opening are communicated at the overlay region;
forming alignment marks in the first alignment opening and the second alignment opening; and
forming a conductive wiring in the first wiring opening and the second wiring opening, wherein the conductive wiring is electrically connected to the integrated circuit component.

### Claim 16 (depends on 15)

The method as claimed in claim 15, wherein the second alignment opening spaced apart from the first alignment opening is formed in the photoresist layer after performing the second development process.

### Claim 17 (depends on 16)

The method as claimed in claim 16, wherein the first alignment mark has an alignment notch, and the second alignment mark extends into the alignment notch.

### Claim 18 (depends on 16)

The method as claimed in claim 16, wherein the second alignment mark has an alignment notch, and the first alignment mark extends into the alignment notch.

### Claim 19 (depends on 15)

The method as claimed in claim 15, wherein the first layout pattern of the first mask comprises a first light-shielding pattern having a first light-transmissive region corresponding to the first wiring opening, and the second layout pattern of the second mask comprises a second light-shielding pattern having a second light-transmissive region corresponding to the second wiring opening.

### Claim 20 (depends on 15)

The method as claimed in claim 15, wherein
the first mask comprises a first overlay area corresponding to the overlay region,
the second mask comprises a second overlay area corresponding to the overlay region,
the first alignment pattern is distributed in the first overlay area of the first mask,
the second alignment pattern is distributed in the second overlay area of the second mask, and
when performing the second exposure process, the second overlay area of the second mask covers the first alignment opening formed in the photoresist layer.