# US 11,908,689 B2 · Method for fabricating GaN chip and GaN chip

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- Number: US 11,908,689 B2
- Document ID: US11908689B2
- Status: Granted
- Kind: B2
- Application number: 18/268,949
- Filed: 2021-10-29
- Published: 2023-12-07
- Granted: 2024-02-20
- Earliest claimed: 2021-07-15
- Assignees: Inspur Suzhou Intelligent Technology Co., Ltd.
- Applicants: Inspur Suzhou Intelligent Technology Co., Ltd.
- Inventors: Fen Guo; Kang Su; Lang Zhou; Tuo Li; Hongtao Man
- Web page: https://patentgrep.com/patent/US11908689B2

## CPC

- H10P 10/12: {Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914)}
- H10P 14/3416: {Nitrides}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 95/11: {Separation of active layers from substrates}
- H10W 20/058: {by depositing on sacrificial masks, e.g. using lift-off}
- H10P 14/2904: {Silicon carbide}
- H10P 14/3202: {Materials thereof}
- H10P 14/3216: {Nitrides}
- H10P 14/3251: {consisting of three or more layers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb2N sacrificial layer; growing a Ta2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta2N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb2N sacrificial layer and the Ta2N sacrificial layer; and transferring remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.

## Claims

### Claim 1

A method for fabricating a GaN chip, comprising:
growing a Nb2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb2N sacrificial layer;
growing a Ta2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta2N sacrificial layer to form a GaN wafer;
bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb2N sacrificial layer and the Ta2N sacrificial layer; and
transferring remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.

### Claim 2 (depends on 1)

The method according to claim 1, wherein growing the Nb2N sacrificial layer on the original substrate comprises:
fabricating the Nb2N sacrificial layer with a thickness of 0-50 nm on the original substrate.

### Claim 3 (depends on 1)

The method according to claim 1, wherein growing the Ta2N sacrificial layer on the GaN insertion layer comprises:
fabricating the Ta2N sacrificial layer with a thickness of 0-50 nm on the GaN insertion layer.

### Claim 4 (depends on 1)

The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises:
coating the first surface of the temporary carrier with an adhesive material, placing the temporary carrier on a hot plate for baking, and then cooling the temporary carrier.

### Claim 5 (depends on 4)

The method according to claim 4, wherein coating the first surface of the temporary carrier with the adhesive material comprises:
coating the first surface of the temporary carrier with the adhesive material by a spin coating method, and controlling a rotation speed to be 1200-3000 rpm and a time to be 30-60 seconds.

### Claim 6 (depends on 4)

The method according to claim 4, wherein placing the temporary carrier on the hot plate for baking comprises:
controlling the temperature of the hot plate to 120° C. and baking for 3 minutes; and
controlling the temperature of the hot plate to 180° C. and baking for 4 minutes.

### Claim 7 (depends on 1)

The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises:
controlling a bonding temperature to 200-350° C. and a bonding force to 1000-2000 N.

### Claim 8 (depends on 1)

The method according to claim 1, wherein removing the Nb2N sacrificial layer and the Ta2N sacrificial layer comprises:
removing the Nb2N sacrificial layer and the Ta2N sacrificial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1.

### Claim 9 (depends on 1)

The method according to claim 1, wherein transferring the remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to the target substrate comprises:
activating the remaining material and the target substrate with nitrogen or oxygen, aligning the activated target substrate with the activated remaining material for attachment, and carrying out annealing.

### Claim 10 (depends on 1)

A chip, fabricated by the method according to claim 1.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the material of the original substrate is one of SiC, GaN, sapphire, diamond, Ga2O3 and AlN.

### Claim 12 (depends on 1)

The method according to claim 1, wherein in the step of growing the Ta2N sacrificial layer on the GaN insertion layer, the Ta2N sacrificial layer with hexagonal crystal structure symmetry is grown on the GaN insertion layer by thin film deposition.

### Claim 13 (depends on 1)

The method according to claim 1, wherein in the step of bonding the GaN wafer with the first surface of the temporary carrier, the wafer bonding is carried out through a wafer bonding machine, a bonding temperature is 150-200° C., a bonding time is 5-10 min, and a pressure is 0.1 MPa.

### Claim 14 (depends on 8)

The method according to claim 8, wherein in the step of removing the Nb2N sacrificial layer and the Ta2N sacrificial layer, the Nb2N sacrificial layer and the Ta2N sacrificial layer are removed by a selective wet chemical etching, the original substrate is separated from the GaN insertion layer after etching.

### Claim 15 (depends on 10)

The chip according to claim 10, wherein growing the Nb2N sacrificial layer on the original substrate comprises:
fabricating a Nb2N sacrificial layer with a thickness of 0-50 nm on the original substrate.

### Claim 16 (depends on 10)

The chip according to claim 10, wherein growing the Ta2N sacrificial layer on the GaN insertion layer comprises:
fabricating the Ta2N sacrificial layer with a thickness of 0-50 nm on the GaN insertion layer.

### Claim 17 (depends on 10)

The chip according to claim 10, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises:
coating the first surface of the temporary carrier with an adhesive material, placing the temporary carrier on a hot plate for baking, and then cooling the temporary carrier.

### Claim 18 (depends on 17)

The chip according to claim 17, wherein coating the first surface of the temporary carrier with the adhesive material comprises:
coating the first surface of the temporary carrier with the adhesive material by a spin coating method, and controlling a rotation speed to be 1200-3000 rpm and a time to be 30-60 seconds.

### Claim 19 (depends on 17)

The chip according to claim 17, wherein placing the temporary carrier on the hot plate for baking comprises:
controlling the temperature of the hot plate to 120° C. and baking for 3 minutes; and
controlling the temperature of the hot plate to 180° C. and baking for 4 minutes.

### Claim 20 (depends on 10)

The chip according to claim 10, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises:
controlling a bonding temperature to 200-350° C. and a bonding force to 1000-2000 N.