# US 11,908,554 B2 · Ultra wideband (UWB) transmitter and receiver circuits

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- Number: US 11,908,554 B2
- Document ID: US11908554B2
- Status: Granted
- Kind: B2
- Application number: 17/593,317
- Filed: 2020-03-18
- Published: 2022-06-02
- Granted: 2024-02-20
- Earliest claimed: 2019-03-18
- Applicants: Frederic Nabki; Dominic Deslandes; Michiel Soer; Gabriel Morin-Laporte; Mohammad Taherzadeh-Sani
- Inventors: Frederic Nabki; Dominic Deslandes; Michiel Soer; Gabriel Morin-Laporte; Mohammad Taherzadeh-Sani
- Web page: https://patentgrep.com/patent/US11908554B2

## CPC

- G16H 10/60: for patient-specific data, e.g. for electronic patient records
- G05F 3/24: wherein the transistors are of the field-effect type only (G05F3/205, G05F3/26, G05F3/30 take precedence)
- G16H 40/20: for the management or administration of healthcare resources or facilities, e.g. managing hospital staff or surgery rooms
- G16H 40/67: for remote operation
- G16H 50/30: for calculating health indices; for individual health risk assessment
- H03F 1/02: Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F 3/24: of transmitter output stages
- H03F 3/245: {with semiconductor devices only}
- H03F 3/301: {CMOS common drain output SEPP amplifiers (H03F3/3008 takes precedence)}
- H03F 3/393: with field-effect devices
- H03F 3/4521: {Complementary long tailed pairs having parallel inputs and being supplied in parallel}
- H03F 3/45237: {Complementary long tailed pairs having parallel inputs and being supplied in series}
- H04B 1/40: Circuits
- H04W 52/029: {reducing the clock frequency of the controller}
- H03F 2200/451: the amplifier being a radio frequency amplifier
- Y02D 30/70: in wireless communication networks
- G16H: HEALTHCARE INFORMATICS, i.e. INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR THE HANDLING OR PROCESSING OF MEDICAL OR HEALTHCARE DATA
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H03F: AMPLIFIERS
- H04B: TRANSMISSION
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Ultra-Wideband (UWB) wireless technology transmits digital data as modulated coded impulses over a very wide frequency spectrum with very low power over a short distance. To support extended operation, particularly with battery power sources, the inventors have established UWB devices which support wake-up from deep sleep modes when these devices exploit low frequency clock sources for ultra-low power consumption. Further, power consumption may be reduced by exploiting transistors or so-called compounded MOSFET structures whose effective gain and output resistance exceeds any single transistor irrespective of length or by employing biasless low power differential (exponential) transconductance stages within operational transconductance amplifiers in order to provide very high gain low power amplification stages. Further, the inventors have established voltage reference sources that consume very low current, a few nA, and ultra-low power low dropout regulators.

## Claims

### Claim 1

A method comprising:
providing at least a DC-DC converter as part of an electronic circuit;
establishing a sleep signal relating to powering down an electronic circuit into a sleep mode;
turning off the DC-DC converter in dependence upon the establishment of the sleep signal;
establishing a synthesized clock counter to count the number of synthesized clock cycles between the moment the sleep signal is raised and the moment the DC-DC converter is turned off;
retaining the value of this synthesized clock counter during the sleep mode; and
subtracting a time value established in dependence upon this retained synthesized clock counter value from a predetermined delay relating to when to wake the electronic circuit out of the sleep mode.

### Claim 2 (depends on 1)

The method according to claim 1, wherein
the DC-DC converter is turned-off upon a predetermined edge of a low frequency clock forming part of the electronic circuit.

### Claim 3 (depends on 2)

The method according to claim 2, wherein
the low frequency clock is at least one of operating at a frequency of 32 kHz and is generated by a crystal oscillator.

### Claim 4

A method comprising:
providing at least a DC-DC converter as part of an electronic circuit;
providing a low frequency oscillator for generating a low frequency clock signal;
providing a phase locked loop (PLL) which receives the low frequency clock signal and generates a high frequency PLL clock signal;
establishing a sleep signal relating to powering down an electronic circuit into a sleep mode where the sleep signal;
turning off the DC-DC converter in dependence upon the establishment of the sleep signal where the turning off of the DC-DC converter is synchronised to an edge of the low frequency clock signal;
establishing a synthesized clock counter to count the number of synthesized clock cycles between the moment the sleep signal is raised and the moment the DC-DC converter is turned off where the synthesized clock cycles are of the high frequency PLL clock signal;
retaining the value of this synthesized clock counter during the sleep mode within a sleep counter circuit forming part of the electronic circuit; and
subtracting with the sleep counter circuit a time value established in dependence upon this retained synthesized clock counter value from a predetermined delay relating to when to turn on the DC-DC converter.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising
turning on the DC-DC converter; wherein
turning on the DC-DC converter is synchronized to another edge of the low frequency clock signal.

### Claim 6

A method comprising:
establishing a synthesized clock counter to count the number of synthesized clock cycles between the moment a sleep signal is raised and the moment a DC-DC converter is turned off where the synthesized clock cycles are of a high frequency phase locked loop (PLL) clock signal generated by a PLL which receives a low frequency clock signal and generates the high frequency PLL clock signal and the sleep signal relates to powering down into a sleep mode an electronic circuit coupled to the DC-DC converter;
retaining the value of this synthesized clock counter during the sleep mode within a sleep counter circuit forming part of the electronic circuit; and
subtracting with the sleep counter circuit a time value established in dependence upon this retained synthesized clock counter value from a predetermined delay relating to when to turn back on the DC-DC converter; wherein
the synthesized clock cycles are of the high frequency PLL clock signal.

### Claim 7 (depends on 6)

The method according to claim 6, wherein
the DC-DC converter is turned off upon establishment of the sleep signal; and
the turning off of the DC-DC converter is synchronized to an edge of the low frequency clock signal.

### Claim 8 (depends on 6)

The method according to claim 6, further comprising
turning on the DC-DC converter; wherein
the turning on of the DC-DC converter is synchronised to another edge of the low frequency clock signal.

### Claim 9 (depends on 6)

The method according to claim 6, wherein
the low frequency clock is generated by a crystal oscillator.