# US 11,908,543 B2 · Latch circuit, transmission circuit including latch circuit, and semiconductor apparatus including transmission circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,543 B2 - Document ID: US11908543B2 - Status: Granted - Kind: B2 - Application number: 17/703,646 - Filed: 2022-03-24 - Published: 2023-04-13 - Granted: 2024-02-20 - Earliest claimed: 2021-10-07 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Eun Ji Choi; Keun Seon Ahn; Kwan Su Shon; Yo Han Jeong - Web page: https://patentgrep.com/patent/US11908543B2 ## CPC - G11C 7/106: {Data output latches} - G11C 7/1087: {Data input latches} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - H03K 3/037: Bistable circuits - H03K 3/356191: {with synchronous operation} - G11C 7/1066: {Output synchronization} - G11C 2207/107: Serial-parallel conversion of data or prefetch - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation. ## Claims ### Claim 1 A latch circuit comprising: a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation; and a second detection unit configured to generate the output signal by detecting the level of the input terminal in response to the control clock signal during a state information read operation, wherein the control clock signal transits repeatedly during the normal read operation, and the control clock signal is fixed to a first logic level during the state information read operation. ### Claim 2 (depends on 1) The latch circuit according to claim 1, wherein the first detection unit is configured to generate the output signal by detecting a level of data, which is input through the input terminal, in response to a rising edge or a falling edge that occurs when the control clock signal transitions. ### Claim 3 (depends on 1) The latch circuit according to claim 1, wherein the state information includes a plurality of data bits for defining at least one of whether a recently input command has been normally performed, whether a previously input command has been normally performed, whether there is an operation currently in progress, and whether there is an operation currently on standby. ### Claim 4 (depends on 3) The latch circuit according to claim 3, wherein the first detection unit is configured to operate as an edge trigger circuit, and wherein the second detection unit is configured to operate as a level trigger circuit. ### Claim 5 A latch circuit comprising: a cross-coupled latch configured to latch a level of an input terminal in response to a transition of a control clock signal and output latched data through an output terminal; and a switching section, connected between the output terminal and the input terminal, configured to output state information, which is input through the input terminal, through the output terminal in response to a state information read signal regardless of a transition of the control clock signal. ### Claim 6 (depends on 5) The latch circuit according to claim 5, wherein the cross-coupled latch is configured to detect the level of the input terminal in response to a rising edge or a falling edge that occurs when the control clock signal transitions. ### Claim 7 (depends on 5) The latch circuit according to claim 5, wherein the state information includes a plurality of data bits for defining at least one of whether a recently input command has been normally performed, whether a previously input command has been normally performed, whether there is an operation currently in progress, and whether there is an operation currently on standby. ### Claim 8 (depends on 5) The latch circuit according to claim 5, wherein the latch circuit is configured to operate as an edge trigger circuit during a normal read operation and is configured to operate as a level trigger circuit during a state information read operation. ### Claim 9 A transmission circuit comprising: a latch circuit configured to: generate output signals by detecting levels of each data, which are input through a plurality of differential input terminals, according to each of a rising edge and a falling edge of control clock signals during a normal read operation, and generate the output signals by detecting a level of state information, which is input through the plurality of differential input terminals, in response to the control clock signals during a state information read operation; and a serializer configured to serialize and output the output signals, wherein the control clock signals transits repeatedly during the normal read operation, and the control clock signals are fixed to a first logic level during the state information read operation. ### Claim 10 (depends on 9) The transmission circuit according to claim 9, further comprising: a driver configured to drive pads of an input/output pad unit according to the output of the serializer. ### Claim 11 (depends on 9) The transmission circuit according to claim 9, further comprising: a division circuit configured to generate multi-phase clock signals by dividing an external clock signal; and a clock control circuit configured to generate the control clock signals having a frequency that is equal to a frequency of the external clock signal by selectively combining the multi-phase clock signals according to a plurality of clock enable signals. ### Claim 12 (depends on 9) The transmission circuit according to claim 9, wherein the latch circuit includes a plurality of latch units, and wherein at least one of the plurality of latch units comprises: a cross-coupled latch configured to latch a level of a first differential input terminal, among the plurality of differential input terminals, in response to a transition of a first control clock signal, among the control clock signals, and configured to output latched data through a first output terminal; and a switching section, connected between the first differential input terminal and the first output terminal, configured to output state information, which is input through the first differential input terminal, through the first output terminal in response to a state information read signal, regardless of the transition of the first control clock signal. ### Claim 13 (depends on 12) The transmission circuit according to claim 12, wherein the cross-coupled latch is configured to detect the level of the first differential input terminal in response to a rising edge or a falling edge that occurs when the first control clock signal transitions. ### Claim 14 (depends on 9) The transmission circuit according to claim 9, wherein the state information includes a plurality of data bits for defining at least one of whether a recently input command has been normally performed, whether a previously input command has been normally performed, whether there is an operation currently in progress, and whether there is an operation currently on standby. ### Claim 15 (depends on 9) The transmission circuit according to claim 9, wherein the latch circuit is configured to operate as an edge trigger circuit during the normal read operation and is configured to operate as a level trigger circuit during the state information read operation. ### Claim 16 A semiconductor apparatus comprising: a memory cell array configured to store normal data; a control circuit configured to generate control signals including multi-phase clock signals in response to an external clock signal and configured to output internally stored state information in response to a state information read command; an input/output pad unit; and a transmission circuit configured to: generate output signals by detecting levels of each of the normal data, which are input through a plurality of differential input terminals, according to each of a rising edge and a falling edge of control clock signals and to output the output signals to an external device through the input/output pad unit during a normal read operation, and generate the output signals by detecting a level of state information, which is input through the plurality of differential input terminals, in response to the control clock signals and to output the output signals to an external device through the input/output pad unit during a state information read operation, wherein the control clock signals transits repeatedly during the normal read operation, and the control clock signals are fixed to a first logic level during the state information read operation. ### Claim 17 (depends on 16) The semiconductor apparatus according to claim 16, wherein the control circuit comprises: a division circuit configured to generate the multi-phase clock signals by phase-separating and dividing the external clock signal. ### Claim 18 (depends on 16) The semiconductor apparatus according to claim 16, wherein the transmission circuit comprises: a latch circuit configured to generate the output signals by detecting the levels of the input data according to the transition of the control clock signals during the normal read operation and configured to generate the output signals by detecting the level of the input state information, regardless of the transition of the control clock signals, during the state information read operation; and a clock control circuit configured to generate the control clock signals having a frequency that is equal to a frequency of the external clock signal by selectively combining the multi-phase clock signals according to a plurality of clock enable signals. ### Claim 19 (depends on 18) The semiconductor apparatus according to claim 18, wherein the latch circuit includes a plurality of latch units, and wherein at least one of the plurality of latch units comprises: a cross-coupled latch configured to latch a level of a first differential input terminal in response to a transition of a first control clock signal, among the control clock signals, and to output a latched signal through a first output terminal; and a switching section connected between the first differential input terminal and the first output terminal, and configured to output a signal, which is input through the first differential input terminal, through the first output terminal in response to a state information read signal regardless of the transition of the first control clock signal. ### Claim 20 (depends on 16) The semiconductor apparatus according to claim 16, wherein the state information includes a plurality of data bits for defining at least one of whether a recently input command has been normally performed, whether a previously input command has been normally performed, whether there is an operation currently in progress, and whether there is an operation currently on standby.