Energy efficient memory array with optimized burst read and write data access

A non-transitory machine-readable storage media having machine-readable instructions that, when executed, cause one or more processors to:

• determine whether burst mode is enabled for writing data to a memory, wherein the memory includes N number of slices, each slice includes M number of columns, and each column includes P number of bit cells coupled to a bit line (BL), an inverse bit line (BL #), write column selectors, and read column selectors, and M bit cells from each slice are controllable by a word line;
• generate a single pre-charge pulse and M word line pulses for the M bit cells of the N number of slices to perform M number of write operations after it is determined that the burst mode is enabled, wherein the single pre-charge pulse is applied to the M bit cells prior to the M word line pulses for the M bit cells;
• determine whether an equalization mode is enabled prior to writing data to the memory;
• and
• for each of the M bit cells, equalize the bit line and the inverse bit line of the bit cell prior to writing data into the bit cell if the equalization mode is enabled.

A system comprising:

• a memory comprising a number M of columns, wherein each column comprises P bit cells coupled to a bit line (BL), an inverse bit line (BL #), write column selectors, and read column selectors, and a bit cell from each of the M columns is coupled to a word line;
• and
• a memory controller coupled to the memory, wherein the memory controller is to:
• determine whether a burst mode is enabled for writing data to the memory;
• and
• perform a write operation for the bit cells coupled to the word line, wherein the write operation comprises application of a single pre-charge pulse to the bit line and inverse bit line of each of the M columns concurrent with equalization of the bit line and inverse bit line of each of the M columns, followed by application of a first pulse to the word line to write to a bit cell of a first column of the M columns, followed by equalization of the bit line and inverse bit line of a second column of the M columns, followed by application of a pulse to the word line to write to a bit cell of the second column of the M columns.