# US 11,908,541 B2 · Processing-in-memory (PIM) systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,541 B2 - Document ID: US11908541B2 - Status: Granted - Kind: B2 - Application number: 17/491,893 - Filed: 2021-10-01 - Published: 2022-01-20 - Granted: 2024-02-20 - Earliest claimed: 2020-01-07 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Choung Ki Song - Web page: https://patentgrep.com/patent/US11908541B2 ## CPC - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G11C 7/1069: {I/O lines read out arrangements} - G11C 7/1096: {Write circuits, e.g. I/O line write drivers} - G11C 11/54: using elements simulating biological cells, e.g. neuron - G06F 2207/4824: Neural networks - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processing-in-memory (PIM) system includes a first and second PIM devices and a host. Each of the first and second PIM devices includes a plurality of multiplying-and-accumulating (MAC) operators and a plurality of memory banks supplying weight data to the plurality of MAC operators. The host controls the first and second PIM devices and includes a data buffer. The first and second PIM devices include a first global buffer and a second global buffer, which supply the vector data to the plurality of MAC operators, respectively. The host reads the vector data out of the first and second PIM devices to store the vector data into the data buffer and writes the vector data stored in the data buffer into the first and second global buffers. ## Claims ### Claim 1 A processing-in-memory (PIM) system comprising: a first PIM device and a second PIM devices, wherein each of the first and second PIM devices includes a plurality of multiplying-and-accumulating (MAC) operators capable of performing a MAC arithmetic operation and a plurality of memory banks capable of supplying weight data to the plurality of MAC operators, and wherein the MAC arithmetic operation is performed using the weight data and vector data as input data; and a host capable of controlling the first and second PIM devices and including a data buffer, wherein the first and second PIM devices include a first global buffer and a second global buffer, which are capable of supplying the vector data to the plurality of MAC operators, respectively, and wherein the host is configured to read the vector data out of the first and second PIM devices to store the vector data into the data buffer and is configured to write the vector data stored in the data buffer into the first and second global buffers. ### Claim 2 (depends on 1) The PIM system of claim 1, wherein the vector data supplied from the first global buffer to the plurality of MAC operators in the first PIM device are the same data as the vector data supplied from the second global buffer to the plurality of MAC operators in the second PIM device. ### Claim 3 (depends on 2) The PIM system of claim 2, wherein the vector data include a first group of vector data and a second group of vector data; and wherein the first group of vector data and the second group of vector data are separately stored into at least one first target memory bank among the plurality of memory banks in the first PIM device and at least one second target memory bank among the plurality of memory banks in the second PIM device, respectively. ### Claim 4 (depends on 3) The PIM system of claim 3, wherein the host is capable of: reading the first group of vector data out of the at least one first target memory bank to store the first group of vector data into the data buffer; and reading the second group of vector data out of the at least one second target memory bank to store the second group of vector data into the data buffer. ### Claim 5 (depends on 4) The PIM system of claim 4, wherein the host is configured to store the first and second groups of vector data in the data buffer into each of the first global buffer and the second global buffer. ### Claim 6 (depends on 5) The PIM system of claim 5, wherein the first PIM device is configured to supply the first and second groups of vector data stored in the first global buffer to each of the plurality of MAC operators in the first PIM device; and wherein the second PIM device is configured to supply the first and second groups of vector data stored in the second global buffer to each of the plurality of MAC operators in the second PIM device. ### Claim 7 (depends on 2) The PIM system of claim 2, wherein the vector data include first, second, third, and fourth groups of vector data; and wherein the first, second, third, and fourth groups of vector data are dispersedly stored into at least one first target memory bank among the plurality of memory banks in the first PIM device and at least one second target memory bank among the plurality of memory banks in the second PIM device. ### Claim 8 (depends on 7) The PIM system of claim 7, wherein the first and third groups of vector data are stored into the at least one first target memory bank, and the second and fourth groups of vector data are stored into the at least one second target memory bank. ### Claim 9 (depends on 8) The PIM system of claim 8, wherein the host is capable of: reading the first and third groups of vector data out of the at least one first target memory bank to store the first and third groups of vector data into the data buffer; and reading the second and fourth groups of vector data out of the at least one second target memory bank to store the second and fourth groups of vector data into the data buffer. ### Claim 10 (depends on 9) The PIM system of claim 9, wherein the host is configured to store the first, second, third, and fourth groups of vector data in the data buffer into each of at least one third target memory bank among the plurality of memory banks in the first PIM device and at least one fourth target memory bank among the plurality of memory banks in the second PIM device. ### Claim 11 (depends on 10) The PIM system of claim 10, wherein the MAC arithmetic operation performed by each of the plurality of MAC operators included in the first and second PIM devices includes a first sub-MAC arithmetic operation and a second sub-MAC arithmetic operation; wherein the first PIM device copies the first and second groups of vector data stored in the at least one third target memory bank into the first global buffer; and wherein the second PIM device copies the first and second groups of vector data stored in the at least one fourth target memory bank into the second global buffer. ### Claim 12 (depends on 11) The PIM system of claim 11, wherein the first PIM device is capable of supplying the first and second groups of vector data copied in the first global buffer to each of the plurality of MAC operators in the first PIM device for the first sub-MAC arithmetic operation; and wherein the second PIM device is capable of supplying the first and second groups of vector data copied in the second global buffer to each of the plurality of MAC operators in the second PIM device for the first sub-MAC arithmetic operation. ### Claim 13 (depends on 12) The PIM system of claim 12, wherein the first PIM device is capable of copying the third and fourth groups of vector data stored in the at least one third target memory bank into the first global buffer after the first sub-MAC arithmetic operation; and wherein the second PIM device is capable of copying the third and fourth groups of vector data stored in the at least one fourth target memory bank into the second global buffer after the first sub-MAC arithmetic operation. ### Claim 14 (depends on 13) The PIM system of claim 13, wherein the first PIM device is capable of supplying the third and fourth groups of vector data copied in the first global buffer to each of the plurality of MAC operators in the first PIM device for the second sub-MAC arithmetic operation; and wherein the second PIM device is capable of supplying the third and fourth groups of vector data copied in the second global buffer to each of the plurality of MAC operators in the second PIM device for the second sub-MAC arithmetic operation. ### Claim 15 A processing-in-memory (PIM) system comprising: a first PIM device and a second PIM devices, wherein each of the first and second PIM devices includes a plurality of multiplying-and-accumulating (MAC) operators capable of performing a MAC arithmetic operation and a plurality of memory banks capable of supplying weight data to the plurality of MAC operators, and wherein the MAC arithmetic operation is performed using the weight data and vector data as input data; a host capable of controlling the first and second PIM devices and including a data buffer; and a memory device configured to communicate with the host, wherein the first and second PIM devices include a first global buffer and a second global buffer, which are capable of supplying the vector data to the plurality of MAC operators, respectively, and wherein the host is configured to read the vector data out of the memory device to store the vector data into the data buffer and is configured to write the vector data stored in the data buffer into the first and second global buffers. ### Claim 16 (depends on 15) The PIM system of claim 15, wherein the vector data supplied from the first global buffer to the plurality of MAC operators in the first PIM device are the same data as the vector data supplied from the second global buffer to the plurality of MAC operators in the second PIM device. ### Claim 17 (depends on 16) The PIM system of claim 16, wherein the memory device is configured to store the vector data; and wherein the vector data include a first group of vector data and a second group of vector data. ### Claim 18 (depends on 17) The PIM system of claim 17, wherein the host is capable of reading the first and second groups of vector data out of the memory device to store the first and second groups of vector data into the data buffer. ### Claim 19 (depends on 18) The PIM system of claim 18, wherein the host is configured to store the first and second groups of vector data in the data buffer into each of the first global buffer and the second global buffer. ### Claim 20 (depends on 19) The PIM system of claim 19, wherein the first PIM device is configured to supply the first and second groups of vector data stored in the first global buffer to each of the plurality of MAC operators in the first PIM device; and wherein the second PIM device is configured to supply the first and second groups of vector data stored in the second global buffer to each of the plurality of MAC operators in the second PIM device. ### Claim 21 (depends on 16) The PIM system of claim 16, wherein the memory device is configured to store the vector data; and wherein the vector data include first, second, third, and fourth groups of vector data. ### Claim 22 (depends on 21) The PIM system of claim 21, wherein the host is capable of reading the first, second, third, and fourth groups of vector data out of the memory device to store the first, second, third, and fourth groups of vector data into the data buffer. ### Claim 23 (depends on 22) The PIM system of claim 22, wherein the host is configured to store the first, second, third, and fourth groups of vector data in the data buffer into each of: at least one third target memory bank among the plurality of memory banks in the first PIM device; and at least one fourth target memory bank among the plurality of memory banks in the second PIM device. ### Claim 24 (depends on 23) The PIM system of claim 23, wherein the MAC arithmetic operation performed by each of the plurality of MAC operators included in the first and second PIM devices includes a first sub-MAC arithmetic operation and a second sub-MAC arithmetic operation; wherein the first PIM device is capable of copying the first and second groups of vector data stored in the at least one third target memory bank into the first global buffer; and wherein the second PIM device is capable of copying the first and second groups of vector data stored in the at least one fourth target memory bank into the second global buffer. ### Claim 25 (depends on 24) The PIM system of claim 24, wherein the first PIM device is capable of supplying the first and second groups of vector data copied in the first global buffer to each of the plurality of MAC operators in the first PIM device for the first sub-MAC arithmetic operation; and wherein the second PIM device is capable of supplying the first and second groups of vector data copied in the second global buffer to each of the plurality of MAC operators in the second PIM device for the first sub-MAC arithmetic operation. ### Claim 26 (depends on 25) The PIM system of claim 25, wherein the first PIM device is capable of copying the third and fourth groups of vector data stored in the at least one third target memory bank into the first global buffer after the first sub-MAC arithmetic operation; and wherein the second PIM device is capable of copying the third and fourth groups of vector data stored in the at least one fourth target memory bank into the second global buffer after the first sub-MAC arithmetic operation. ### Claim 27 (depends on 26) The PIM system of claim 26, wherein the first PIM device is capable of supplying the third and fourth groups of vector data copied in the first global buffer to each of the plurality of MAC operators in the first PIM device for the second sub-MAC arithmetic operation; and wherein the second PIM device is capable of supplying the third and fourth groups of vector data copied in the second global buffer to each of the plurality of MAC operators in the second PIM device for the second sub-MAC arithmetic operation.