# US 11,908,538 B2 · Cell structures and power routing for integrated circuits

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- Number: US 11,908,538 B2
- Document ID: US11908538B2
- Status: Granted
- Kind: B2
- Application number: 17/127,091
- Filed: 2020-12-18
- Published: 2021-09-02
- Granted: 2024-02-20
- Earliest claimed: 2020-02-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shih-Wei Peng; Jiann-Tyng Tzeng; Kam-Tou Sio
- Web page: https://patentgrep.com/patent/US11908538B2

## CPC

- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/00: Interconnections or connectors in packages
- G11C 11/412: using field-effect transistors only
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.

## Claims

### Claim 1

A cell in an integrated circuit, the cell comprising:
a first conductor layer comprising a conductor stripe divided into multiple conductor segments and a first power stripe that is configured to connect to a first voltage source to provide a first voltage signal;
a second conductor layer overlying the first conductor layer and comprising a second power stripe and one or more conductor pillars, wherein the second power stripe is configured to connect to a second voltage source to provide a second voltage signal, wherein a first conductor segment in the multiple conductor segments is electrically connected to the second power stripe to provide the second voltage signal to the first conductor layer in the cell, and wherein each conductor pillar is electrically connected to the first power stripe; and
a third conductor layer disposed between the first and second conductor layers, the third conductor layer providing one or more contacts between the first and the second conductor layers.

### Claim 2 (depends on 1)

The cell of claim 1, wherein a second conductor segment in the multiple conductor segments in the first conductor layer is configured as a signal line.

### Claim 3 (depends on 1)

The cell of claim 1, wherein the first power stripe extends outside a boundary of the cell and is shared by an adjacent cell that abuts the cell.

### Claim 4 (depends on 1)

The cell of claim 1, wherein the second power stripe extends outside a boundary of the cell and is shared by an adjacent cell that abuts the cell.

### Claim 5 (depends on 1)

The cell of claim 1, further comprising:
a first active diffusion region disposed below the first conductor layer;
a second active diffusion region disposed below the first conductor layer;
one or more metal-to-diffusion (MD) regions disposed over the first and the second active diffusion regions; and
one or more poly lines disposed over the first and the second active diffusion regions.

### Claim 6 (depends on 1)

The cell of claim 1, wherein a cell height of the cell is in a range of approximately one hundred to one hundred and thirty nanometers.

### Claim 7

An integrated circuit, comprising:
a first cell comprising a first metal layer comprising a first power stripe that is operable to connect to a first voltage source to supply a first voltage signal and a first metal stripe divided into multiple metal segments,
wherein a first metal segment in the multiple metal segments extends outside a boundary of the first cell and is operable to supply a second voltage signal to the first cell;
a second cell adjacent the first cell, the second cell comprising the first metal layer comprising the first power stripe that is operable to supply the first voltage signal and a second metal stripe divided into multiple metal segments,
wherein a second metal segment in the multiple metal segments extends outside a boundary of the second cell and is operable to supply the second voltage signal to the second cell, and
wherein the second metal segment includes one or more conductor pillars each connected to the first power stripe,
wherein the first metal segment and the second metal segment form one metal segment that resides between and in the first and the second cells.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, further comprising:
a third metal segment in the multiple metal segments in the first cell that is used for a first signal.

### Claim 9 (depends on 7)

The integrated circuit of claim 7, wherein:
the first power stripe extends outside the cell boundary of the first cell and is shared by a third cell that abuts the first cell.

### Claim 10 (depends on 7)

The integrated circuit of claim 7, further comprising a filler cell that is disposed between the first cell and the second cell, wherein the one metal segment formed by the first metal segment and the second metal segment resides in the filler cell.

### Claim 11 (depends on 7)

The integrated circuit of claim 7, wherein:
the first cell further comprises a second metal layer overlying the first metal layer and comprising a second power stripe that is operable to connect to the second voltage source to provide the second voltage signal, wherein the second power stripe is electrically connected to the first metal segment in the first metal layer.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein:
the second power stripe extends outside the boundary of the first cell and is shared by a third cell that abuts the first cell; and
the second power stripe extends outside the boundary of the second cell and is shared by a fourth cell that abuts the second cell.

### Claim 13

A method of fabricating an integrated circuit, the method comprising:
forming a first conductor layer over the integrated circuit, wherein the first conductor layer includes a conductor stripe that is divided into multiple conductor segments and a first power stripe that is configured to provide a first voltage signal;
forming a contact layer overlying the first conductor layer;
forming a second conductor layer overlying the contact layer and comprising a second power stripe and one or more conductor pillars, wherein the second power stripe is configured to provide a second voltage signal, wherein a contact in the contact layer electrically connects a first conductor segment in the multiple conductor segments to the second power stripe to provide the second voltage signal to the first conductor layer, and wherein each conductor pillar is electrically connected to the first power stripe,
forming a third conductor layer disposed between the first and second conductor layers, the third conductor layer providing one or more contacts between the first and the second conductor layers.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first conductor segment is formed to extend beyond a boundary of a cell in the integrated circuit.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
forming one or more active regions in a substrate;
forming a poly layer over the one or more active regions, the poly layer comprising a poly line; and
forming a metal-to-diffusion (MD) layer over the one or more active regions, the MD layer comprising a MD region.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a via-to-diffusion (VD) layer over the MD layer, the VD layer comprising a VD region that is formed over the MD region;
forming a via-to-gate (VG) layer over the poly layer, the VG layer comprising a VG region that is formed over the poly line, wherein the first conductor layer is formed over the VD and the VG layers.

### Claim 17 (depends on 13)

The method of claim 13, wherein forming the first conductor layer over the integrated circuit comprises forming the first conductor layer over the integrated circuit,
wherein the first conductor layer includes a first conductor stripe that is divided into multiple conductor segments, the second power stripe that is configured to provide the first voltage signal, and a second conductor stripe that is configured as a signal line.

### Claim 18 (depends on 8)

The integrated circuit of claim 8, further comprising:
a fourth metal segment in the multiple metal segments in the second cell that is used for a first signal.

### Claim 19 (depends on 10)

The integrated circuit of claim 10, wherein:
the first power stripe extends outside the cell boundary of the second cell and is shared by a fourth cell that abuts the second cell.

### Claim 20 (depends on 11)

The integrated circuit of claim 11, wherein:
the second cell further comprises the second metal layer overlying the first metal layer and comprising the second power stripe that provides the second voltage signal, wherein the second power stripe is electrically connected to the second metal segment in the first metal layer.