# US 11,908,535 B2 · Memory device and memory controller and storage device including the memory device and memory controller > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,535 B2 - Document ID: US11908535B2 - Status: Granted - Kind: B2 - Application number: 17/540,535 - Filed: 2021-12-02 - Published: 2022-06-30 - Granted: 2024-02-20 - Earliest claimed: 2020-12-29 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jinmin Seok; Jonghwa Kim - Web page: https://patentgrep.com/patent/US11908535B2 ## CPC - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 29/4401: {for self repair} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 29/025: {in signal lines} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 29/72: {with optimized replacement algorithms} - G11C 29/76: {using address translation or modifications} - G11C 29/81: {using a hierarchical redundancy scheme} - G06F 2212/1016: Performance improvement - G06F 2212/7204: Capacity control, e.g. partitioning, end-of-life degradation - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Provided are a memory device and a memory controller, which are configured to repair a weak word line, and a method of operating a storage device including the memory device and the memory controller. A memory device includes a memory cell array including a plurality of normal word lines and at least one spare word line, and a repair controller configured to set memory cells connected to at least one weak word line to a first operation mode and further configured to set memory cells connected to the at least one spare word line to a second operation mode. The at least one weak word line is detected from among the normal word lines based on a test result. ## Claims ### Claim 1 A memory device comprising: a memory cell array comprising a plurality of normal word lines and at least one spare word line; and a repair controller configured to set memory cells which are connected to at least one weak word line from among the normal word lines to a first operation mode, and further configured to set memory cells connected to the at least one spare word line to a second operation mode, wherein the at least one weak word line is detected based on a test result, wherein, during a test process, memory cells connected to the plurality of normal word lines are set to a third operation mode configured to write (n+m)-bit data, the first operation mode is configured to write n-bit data to the memory cells connected to the at least one weak word line, the second operation mode is configured to write m-bit data to the memory cells connected to the at least one spare word line, and both n and m are natural numbers greater than or equal to 1 and m is greater than n. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the at least one weak word line includes a plurality of weak memory cells, wherein a number of weak memory cells included in each of the at least one weak word line is greater than or equal to a reference number. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the memory cell array, comprises a meta region configured to store metadata, wherein the repair controller stores a cell operation mode of the at least one weak word line and a cell operation mode of the at least one spare word line in the meta region. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the memory device receives a command from a memory controller and performs an operation in response to the command, based on the cell operation mode stored in the meta region. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the first operation mode is a single-level cell (SLC) mode, the second operation mode is a multi-level cell (MLC) mode, and the third operation mode is a triple-level cell (TLC) mode. ### Claim 6 A memory controller connected to a memory device comprising a plurality of normal word lines and at least one spare word line, wherein the memory controller is configured to: transmit a command to the memory device, detect at least one of the normal word lines as a weak word line, when an operation performed in response to the command fails, set memory cells connected to the weak word line to a single-level cell (SLC) operation mode, and set memory cells connected to the at least one spare word line to a multi-level cell (MLC) operation mode, wherein memory cells connected to the plurality of normal word lines are set to a third operation mode configured to write (n+m)-bit data, and wherein the first operation mode is configured to write n-bit data to the memory cells connected to the weak word line, the second operation mode is configured to write m-bit data to the memory cells connected to the at least one spare word line, and each of n and m is a natural number greater than or equal to 1 and m is greater than n. ### Claim 7 (depends on 6) The memory controller of claim 6, further comprising a buffer memory including logical addresses, physical addresses, and operation mode information of the memory cells connected to the weak word line, and further including logical addresses, physical addresses, and operation mode information of the memory cells connected to the at least one spare word line. ### Claim 8 (depends on 7) The memory controller of claim 7, wherein the memory controller is configured to transmit a repair copy command to the memory device and to store existing data, the existing data stored in the memory cells connected to the weak word line, in at least one of memory cells connected to the normal word lines and the memory cells connected to the at least one spare word line. ### Claim 9 (depends on 8) The memory controller of claim 8, wherein the memory controller is configured to receive the existing data, the existing data stored in the memory cells connected to the weak word line, from the memory device in response to the repair copy command, and further configured to temporarily store the existing data in the buffer memory, and transmit the existing data to the memory device. ### Claim 10 (depends on 7) The memory controller of claim 7, wherein the memory controller is configured to generate the logical addresses of the memory cells connected to the at least one spare word line, and to map the logical address to the physical addresses of the memory cells connected to the at least one spare word line. ### Claim 11 (depends on 7) The memory controller of claim 7, wherein the memory controller is configured to transmit a cell operation mode control signal including the operation mode information of the memory cells connected to the weak word line and the operation mode information of the memory cells connected to the at least one spare word line to the memory device. ### Claim 12 (depends on 7) The memory controller of claim 7, wherein the memory controller is configured to convert a command and an address in response to a request received from a host, based on the operation mode information of the memory cells connected to the weak word line and the operation mode information of the memory cells connected to the at least one spare word line, and to transmit the converted command and the converted address to the memory device. ### Claim 13 (depends on 6) The memory controller of claim 6, wherein the memory controller is configured to detect a normal word line including at least a reference number of weak memory cells as the weak word line, based on a number of weak memory cells included in each of the normal word lines. ### Claim 14 (depends on 13) The memory controller of claim 13, wherein the command comprises a write command or an erase command. ### Claim 15 A method of operating a storage device comprising a memory device and a memory controller, the memory device comprising a plurality of normal word lines and at least one spare word line, the method comprising: detecting at least one of the normal word lines as a weak word line; setting an operation mode of memory cells connected to the weak word line to a first operation mode and setting an operation mode of memory cells connected to the at least one spare word line to a second operation mode; receiving a write request from a host; and writing data to at least one of the memory cells connected to the weak word line and the memory cells connected to the at least one spare word line, based on the set operation mode, wherein memory cells connected to the plurality of normal word lines are set to a third operation mode configured to write (n+m)-bit data, and wherein the first operation mode is configured to write n-bit data to the memory cells connected to the weak word line, the second operation mode is configured to write m-bit data to the memory cells connected to the at least one spare word line, and each of n and m is a natural number greater than or equal to 1 and m is greater than n. ### Claim 16 (depends on 15) The method of claim 15, wherein the detecting of the at least one of the normal word lines as the weak word line comprises detecting a word line including at least a reference number of weak memory cells as the weak word line, wherein a weak memory cell is a memory cell that has failed a write operation or an erase operation, from among memory cells connected to the normal word lines. ### Claim 17 (depends on 15) The method of claim 15, wherein the setting of the operation mode of the memory cells connected to the spare word line to the second operation mode comprises storing first operation mode information and second operation mode information in at least one of a buffer memory of the memory controller and a meta region of the memory device. ### Claim 18 (depends on 15) The method of claim 15, wherein the writing of the data comprises writing the data to the memory cells connected to the weak word line in a single-level cell (SIC) mode or writing the data to the memory cells connected to the spare word line in a multi-level cell (MLC) mode.