# US 11,908,532 B2 · Memory device and method of operating the memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,532 B2 - Document ID: US11908532B2 - Status: Granted - Kind: B2 - Application number: 17/580,274 - Filed: 2022-01-20 - Published: 2023-02-09 - Granted: 2024-02-20 - Earliest claimed: 2021-08-04 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jong Woo Kim; Young Cheol Shin - Web page: https://patentgrep.com/patent/US11908532B2 ## CPC - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation for storing data in selected memory cells among the plurality of memory cells, and a control logic circuit configured to control the peripheral circuit to form threshold voltage distributions corresponding to target program states corresponding to the data to be stored in the selected memory cells, respectively, wherein the control logic controls the peripheral circuit to perform a main verify operation for any one of the target program states of the selected memory cells when a pre-verify operation for the any one of the target program states has passed. ## Claims ### Claim 1 A memory device, comprising: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation including a plurality of program loops for storing data in selected memory cells among the plurality of memory cells; and a control logic circuit configured to control the peripheral circuit to perform a program verify operation including one of a main verify operation and a pre-verify operation, the program verify operation verifying whether the selected memory cells form threshold voltage distributions corresponding to target program states corresponding to the data to be stored in the selected memory cells, respectively, wherein the control logic circuit, when the pre-verify operation for any one of the target program states has passed in any one of the plurality of program loops has passed, controls the peripheral circuit to perform the main verify operation for the any one of the target program states of the selected memory cells in a next program loop of the any one of the plurality of program loops. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein the control logic circuit, when the pre-verify operation for the any one of the target program states has passed in the any one of the plurality of program loops has passed, controls the peripheral circuit to skip the pre-verify operation for the any one of the target program states in the next program loop. ### Claim 3 (depends on 1) The memory device according to claim 1, wherein the pre-verify operation is determined to have failed when a number of memory cells having threshold voltages lower than a pre-verify voltage is greater than a reference number of memory cells. ### Claim 4 (depends on 1) The memory device according to claim 1, wherein the main verify operation is determined to have failed when a number of memory cells having threshold voltages lower than a main verify voltage is greater than a reference number of memory cells. ### Claim 5 (depends on 4) The memory device according to claim 4, wherein the main verify voltage has a potential level higher than a potential level of a pre-verify voltage. ### Claim 6 (depends on 1) The memory device according to claim 1, wherein the control logic circuit comprises: a program loop manager configured to generate pre-pass information related to a program loop in which the pre-verify operation has passed and main pass information related to a program loop in which the main verify operation has passed. ### Claim 7 (depends on 6) The memory device according to claim 6, wherein the control logic circuit controls a subsequent program operation on memory cells to be programmed after the selected memory cells, based on the pre-pass information and the main pass information. ### Claim 8 (depends on 1) The memory device according to claim 1, wherein the program operation is an incremental step pulse programming operation in which a program voltage to be applied is increased by a step voltage as the plurality of program loops are sequentially performed. ### Claim 9 (depends on 1) The memory device according to claim 1, wherein the control logic circuit comprises: a program voltage controller configured to control the peripheral circuit to apply a program voltage to a word line coupled to the selected memory cells; and a verify operation controller configured to control the peripheral circuit to apply a main verify voltage for the main verify operation or a pre-verify voltage for the pre-verify operation to the word line coupled to the selected memory cells. ### Claim 10 (depends on 1) The memory device according to claim 1, wherein the peripheral circuit comprises: a voltage generator configured to generate internal voltages including a program voltage, a main verify voltage, and a pre-verify voltage that are applied during the program operation. ### Claim 11 A memory device, comprising: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation including a plurality of program loops for storing data in selected memory cells among the plurality of memory cells; and a control logic circuit configured to control the peripheral circuit to perform a program verify operation including a main verify operation and a pre-verify operation, the program verify operation verifying whether the selected memory cells form threshold voltage distributions corresponding to target program states corresponding to the data to be stored in the selected memory cells, respectively, wherein the control logic circuit, when the pre-verify operation for any one of the target program states of the selected memory cells in any one of the plurality of program loops has passed, controls the peripheral circuit to skip the pre-verify operation for the any one of the target program states in next program loop of the any one of the plurality of program loops. ### Claim 12 (depends on 11) The memory device according to claim 11, wherein the control logic circuit, when the pre-verify operation for the any one of the target program states has passed, controls the peripheral circuit to perform only the main verify operation for the any one of the target program states. ### Claim 13 (depends on 11) The memory device according to claim 11, wherein the pre-verify operation is determined to have failed when a number of memory cells having threshold voltages lower than a pre-verify voltage is greater than a reference number of memory cells. ### Claim 14 (depends on 11) The memory device according to claim 11, wherein the main verify operation is determined to have failed when a number of memory cells having threshold voltages lower than a main verify voltage is greater than a reference number of memory cells. ### Claim 15 (depends on 14) The memory device according to claim 14, wherein the main verify operation uses the main verify voltage having a potential level higher than a potential level of a pre-verify voltage for the pre-verify operation. ### Claim 16 (depends on 11) The memory device according to claim 11, wherein the control logic circuit comprises: a program loop manager configured to generate pre-pass information related to a program loop in which the pre-verify operation has passed and main pass information related to a program loop in which the main verify operation has passed. ### Claim 17 (depends on 16) The memory device according to claim 16, wherein the control logic circuit controls a subsequent program operation on memory cells to be programmed after the selected memory cells, based on the pre-pass information and the main pass information. ### Claim 18 (depends on 11) The memory device according to claim 11, wherein the program operation is an incremental step pulse programming operation in which a program voltage to be applied is increased by a step voltage as the plurality of program loops are sequentially performed. ### Claim 19 (depends on 11) The memory device according to claim 11, wherein the control logic circuit comprises: a program voltage controller configured to control the peripheral circuit to apply a program voltage to a word line coupled to the selected memory cells; and a verify operation controller configured to control the peripheral circuit to apply a main verify voltage for the main verify operation and a pre-verify voltage for the pre-verify operation to the word line coupled to the selected memory cells. ### Claim 20 (depends on 11) The memory device according to claim 11, wherein the peripheral circuit comprises: a voltage generator configured to generate internal voltages including a program voltage, a main verify voltage, and a pre-verify voltage that are applied during the program operation.