# US 11,908,531 B2 · Detecting and managing under-program failures in non-volatile memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,531 B2 - Document ID: US11908531B2 - Status: Granted - Kind: B2 - Application number: 17/495,574 - Filed: 2021-10-06 - Published: 2023-04-06 - Granted: 2024-02-20 - Earliest claimed: 2021-10-06 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Nikolaos Papandreou; Roman Alexander Pletka; Radu Ioan Stoica; Nikolas Ioannou; Charalampos Pozidis; Timothy J. Fisher; Aaron Daniel Fry - Web page: https://patentgrep.com/patent/US11908531B2 ## CPC - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells} - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2029/0409: {Online test} - G11C 2029/0411: {Online error correction} - G11C 2211/5644: Multilevel memory comprising counting devices - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error. ## Claims ### Claim 1 A method of controlling a non-volatile memory including a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages, the method comprising: a controller of the non-volatile memory issuing a command to perform a programming pass for a physical page among the multiple physical pages; the controller determining whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received; and based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detecting an under-programming error and performing mitigation for the detected under-programming error. ### Claim 2 (depends on 1) The method of claim 1, wherein: the non-volatile memory includes an integrated circuit including a plurality of physical layers; the method further comprises the controller determining the minimum threshold time based on which of the plurality of physical layers includes the physical page. ### Claim 3 (depends on 1) The method of claim 1, wherein: the controller programs the physical pages in a plurality of programming passes including the programming pass; and the method further comprises the controller determining the minimum threshold time based on which of the plurality of programming passes the programming pass is. ### Claim 4 (depends on 1) The method of claim 1, wherein: the multiple physical pages are of a plurality of different page types; the method further comprises the controller determining the minimum threshold time based on a page type of the physical page. ### Claim 5 (depends on 1) The method of claim 1, wherein the method further comprises: the controller determining the minimum threshold time based on a program/erase (P/E) cycle count of a block containing the physical page. ### Claim 6 (depends on 1) The method of claim 1, wherein: the non-volatile memory includes an integrated circuit including a plurality of physical layers; performing mitigation includes the controller programming data intended for the physical page into a different one of the plurality of physical layers. ### Claim 7 (depends on 6) The method of claim 6, wherein: the plurality of physical layers includes a particular layer; and performing mitigation further includes relocating valid data from the particular layer, writing dummy data to non-programmed physical pages in the particular layer, and invalidating valid physical pages in the particular layer. ### Claim 8 A computer program product, the computer program product comprising a computer readable storage device having program instructions embodied therewith, the program instructions being executable by a controller of a non-volatile memory including a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page, wherein, when executed, the program instructions cause the controller to perform: issuing a command to perform a programming pass for a physical page among the multiple physical pages; determining whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received; and based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, detecting an under-programming error and performing mitigation for the detected under-programming error. ### Claim 9 (depends on 8) The computer program product of claim 8, wherein: the non-volatile memory includes an integrated circuit including a plurality of physical layers; the program instructions cause the controller to perform determining the minimum threshold time based on which of the plurality of physical layers includes the physical page. ### Claim 10 (depends on 8) The computer program product of claim 8, wherein: the controller programs the physical pages in a plurality of programming passes including the programming pass; and the program instructions cause the controller to perform determining the minimum threshold time based on which of the plurality of programming passes the programming pass is. ### Claim 11 (depends on 8) The computer program product of claim 8, wherein: the multiple physical pages are of a plurality of different page types; the program instructions cause the controller to perform determining the minimum threshold time based on a page type of the physical page. ### Claim 12 (depends on 8) The computer program product of claim 8, wherein the controller is further configured to perform: determining the minimum threshold time based on a program/erase (P/E) cycle count of a block containing the physical page.