# US 11,908,527 B2 · Memory device and method of operating the memory device

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- Number: US 11,908,527 B2
- Document ID: US11908527B2
- Status: Granted
- Kind: B2
- Application number: 17/682,362
- Filed: 2022-02-28
- Published: 2023-03-16
- Granted: 2024-02-20
- Earliest claimed: 2021-09-15
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dong Jae Jung; Sung Won Bae
- Web page: https://patentgrep.com/patent/US11908527B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F 11/1044: {with specific ECC/EDC distribution}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present technology relates to an electronic device. According to the present technology, a memory device may include memory cells respectively connected to a plurality of word lines, a peripheral circuit configured to perform a read operation of reading data stored in selected memory cells connected to a selected word line among the memory cells, and a read operation controller configured to control the peripheral circuit to apply a pass voltage to adjacent word lines adjacent to the selected word line during the read operation, discharge the pass voltage to a target pass voltage less than the pass voltage after a predetermined time elapses, and obtain data stored in the selected memory cells through bit lines connected to the selected memory cells after a target read time elapses, after a voltage applied to the adjacent word lines is discharged to the target pass voltage.

## Claims

### Claim 1

A memory device comprising:
a plurality of memory cells respectively connected to a plurality of word lines;
a peripheral circuit configured to perform a read operation of reading data stored in selected memory cells among the plurality of memory cells, the selected memory cells connected to a selected word line among the plurality of word lines; and
a read operation controller configured to control the peripheral circuit to apply a pass voltage to adjacent word lines among the plurality of word lines adjacent to the selected word line during the read operation, discharge the pass voltage to a target pass voltage less than the pass voltage after a predetermined time elapses, and after a target read time elapses from when the pass voltage is discharged to the target pass voltage, obtain data stored in the selected memory cells through bit lines connected to the selected memory cells.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the read operation controller comprises:
an open read information storage configured to store pass voltage magnitude information which is information on magnitudes of the pass voltage and the target pass voltage; and
a read voltage controller configured to determine the magnitudes of the pass voltage and the target pass voltage based on the pass voltage magnitude information.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the open read information storage further comprises pass voltage time information which is information on the predetermined time, and
the read voltage controller determines a time when the pass voltage is applied to the adjacent word lines based on the pass voltage time information.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the read operation controller comprises a page buffer controller that controls page buffers connected to the bit lines to sense a potential of the bit lines after the target read time elapses.

### Claim 5 (depends on 2)

The memory device of claim 2, wherein when a read fail occurs in the read operation, the read operation controller controls the peripheral circuit to further increase the target read time by a step read time in response to a read time change command of a memory controller, and perform the read operation by applying a read time changed according to the read time change command in response to a read command provided from the memory controller.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the open read information storage further comprises read time information including information on the target read time and the step read time.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the selected memory cells each include a memory cell configured to store one bit of data.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the target pass voltage is a minimum voltage for forming a channel through which a current flows in a channel region of memory cells connected to the adjacent word lines.

### Claim 9 (depends on 1)

The memory device of claim 1,
wherein the selected word line is in an open state.

### Claim 10

A storage device comprising:
a memory device including a memory block including memory cells; and
a memory controller comprising an operation controller configured to output a read command and an address for the memory cells, and provide an open read command and the address to the memory device when a read operation performed by the memory device in response to the read command has failed,
wherein in response to the open read command, the memory device applies a pass voltage to adjacent word lines adjacent to a selected word line including the memory cells, discharges the pass voltage to a target pass voltage less than the pass voltage by a step voltage after a predetermined time elapses and, after a target read time elapses from when the pass voltage is discharged to the target pass voltage, obtains data stored in the memory cells through bit lines connected to the memory cells.

### Claim 11 (depends on 10)

The storage device of claim 10, wherein when the open read operation has failed, the operation controller provides a read time change command for further increasing the target read time by a step read time to the memory device, and then provides the open read command for causing the memory device to perform the open read operation by applying a changed target read time according to the read time change command to the memory device.

### Claim 12 (depends on 11)

The storage device of claim 11, wherein the operation controller repeatedly provides the read time change command and the open read command to the memory device until the open read operation for the memory cells has passed.

### Claim 13 (depends on 10)

The storage device of claim 10, wherein the memory controller further comprises an error correction circuit that corrects an error bit of data read in the read operation or the open read operation, determines whether the read operation or the open read operation has passed or failed by comparing the number of error bits of the read data with the number of correctable error bits, and provides information on whether the read operation or the open read operation has passed or failed to the operation controller.

### Claim 14 (depends on 13)

The storage device of claim 13, wherein the memory device comprises a plurality of memory blocks, and
the memory controller further comprises a bad block information storage that stores bad block information which is information on bad blocks on which a memory operation is limited among the plurality of memory blocks.

### Claim 15 (depends on 14)

The storage device of claim 14, wherein when the open read operation has passed, the operation controller provides a program command to the memory device for causing the memory device to store data, which is stored in a first memory block including the memory cells, in a second memory block except for bad blocks among the plurality of memory blocks, and
the memory device programs the data stored in the first memory block to the second memory block in response to the program command.

### Claim 16 (depends on 10)

The storage device of claim 10, wherein the memory device further comprises an open read information storage including pass voltage information that includes pass voltage magnitude information which is information on magnitudes of the pass voltage and the target pass voltage, information on the predetermined time, and information on the step voltage, and
the operation controller provides a command for changing at least one of the pass voltage magnitude information, the information on the predetermined time, and the information on the step voltage to the memory device.

### Claim 17

A method of operating a storage device for performing a read operation of reading data stored in selected memory cells connected to a selected word line among a plurality of word lines included in a target memory block among a plurality of memory blocks, the method comprising:
applying a pass voltage to word lines adjacent to the selected word line;
discharging the pass voltage to a target pass voltage less than the pass voltage;
sensing a potential of bit lines connected to the selected memory cells connected to the selected word line after the pass voltage is discharged to the target pass voltage and a target read time elapses; and
determining whether the read operation has passed or failed by comparing the number of error bits of read data with the number of correctable error bits with respect to the selected memory cells.

### Claim 18 (depends on 17)

The method of claim 17, wherein discharging the pass voltage to the target pass voltage comprises decreasing the pass voltage by a step voltage every predetermined time until a magnitude of the pass voltage reaches the target pass voltage.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
repeatedly performing the read operation by increasing the target read time by a step read time until the read operation on the selected memory cells is passed when the read operation has failed.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
storing data, which is stored in the selected memory cells, in a memory block except for the target memory block when the read operation has passed.