# US 11,908,525 B2 · Nonvolatile semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,525 B2 - Document ID: US11908525B2 - Status: Granted - Kind: B2 - Application number: 17/340,310 - Filed: 2021-06-07 - Published: 2021-09-23 - Granted: 2024-02-20 - Earliest claimed: 2010-11-29 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Takashi Maeda - Web page: https://patentgrep.com/patent/US11908525B2 ## CPC - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells - H02J 50/12: of the resonant type - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - B60L 53/38: specially adapted for charging by inductive energy transfer - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - G11C 7/14: Dummy cell management; Sense reference voltage generators - G11C 16/30: Power supply circuits - G11C 16/32: Timing circuits - G11C 2216/16: Flash programming of all the cells in an array, sector or block simultaneously - H02J 2105/37: exchanging power with electric vehicles [EV] or with hybrid electric vehicles [HEV] - G11C: STATIC STORES (semiconductor memory devices H10B) - H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY - H10B: ELECTRONIC MEMORY DEVICES - B60L: PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES (arrangements or mounting of electrical propulsion units or of plural diverse prime-movers for mutual or common propulsion in vehicles B60K1/00, B60K6/20; arrangements or mounting of electrical gearing in vehicles B60K17/12, B60K17/14; preventing wheel slip by reducing power in rail vehicles B61C15/08; dynamo-electric machines H02K; control or regulation of electric motors H02P); SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES (electric coupling devices combined with mechanical couplings of vehicles B60D1/64; electric heating for vehicles B60H1/00); ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL (control or regulation of electric motors H02P); MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES ## Abstract When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. ## Claims ### Claim 1 A method for controlling a memory device, the memory device, including: a memory cell array including a memory block, the memory block including a first sub memory block and a second sub memory block, the first sub memory block including a plurality of first memory cells, and the second sub memory block including a plurality of second memory cells; a first drain side selective transistor connected to the first memory cells; a second drain side selective transistor connected to the second memory cells; a first source side selective transistor connected to the first memory cells; a second source side selective transistor connected to the second memory cells; a first source line connected to the first source side selective transistor and the second source side selective transistor; a plurality of first word lines connected to gates of the first memory cells; a plurality of second word lines connected to gates of the second memory cells; a plurality of first control gate lines connected to the plurality of first word lines not via any of the plurality of the second word lines; a plurality of second control gate lines connected to the plurality of second word lines not via any of the plurality of the first word lines; a first source side select gate line connected to a gate of the first source side selective transistor; and a second source side select gate line connected to a gate of the second source side selective transistor; the method including: performing an erase operation of erasing data stored in the plurality of first memory cells in the first sub memory block, while erasing data stored in the plurality of second memory cells in the second sub memory block being prohibited. ### Claim 2 (depends on 1) The method for controlling the memory device according to claim 1, wherein the first source side select gate line and the second source side select gate line are electrically disconnected from each other and capable to apply a voltage independently. ### Claim 3 (depends on 1) The method for controlling the memory device according to claim 1, further comprising: a plurality of third memory cells connected between the first drain side selective transistor and the first source side selective transistor; a first joining portion joining the first memory cells and the third memory cells in series; a plurality of fourth memory cells connected between the second drain side selective transistor and the second source side selective transistor; and a second joining portion joining the second memory cells and the fourth memory cells in series. ### Claim 4 (depends on 1) The method for controlling the memory device according to claim 1, wherein one of the first word lines and a corresponding one of the second word lines are disposed in the same layer, respectively. ### Claim 5 (depends on 1) The method for controlling the memory device according to claim 1, wherein one of the first word lines and a corresponding one of the second word lines are electrically disconnected from each other. ### Claim 6 (depends on 3) The method for controlling the memory device according to claim 3, wherein the first joining portion and the second joining portion, include poly silicon. ### Claim 7 (depends on 3) The method for controlling the memory device according to claim 3, wherein the plurality of first memory cells are arranged in one straight line, the plurality of third memory cells are arranged in another straight line. ### Claim 8 (depends on 3) The method for controlling the memory device according to claim 3, wherein the plurality of first memory cells are arranged in one straight line, the plurality of third memory cells are arranged in another straight line parallel to the one straight line. ### Claim 9 (depends on 3) The method for controlling the memory device according to claim 3, wherein the plurality of first memory cells and the plurality of third memory cells are approximately arranged in one straight line. ### Claim 10 (depends on 1) The method for controlling the memory device according to claim 1, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, and the first voltage is lower than the second voltage. ### Claim 11 (depends on 1) The method for controlling the memory device according to claim 1, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, and a timing of applying the first voltage is later than a timing of applying the second voltage. ### Claim 12 (depends on 1) The method for controlling the memory device according to claim 1, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, applying a third voltage to the first source line, the first voltage is lower than the third voltage. ### Claim 13 (depends on 1) The method for controlling the memory device according to claim 1, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, applying a third voltage to the first source line, the first voltage is lower than the third voltage, a timing of applying the third voltage is earlier than a timing of applying the first voltage. ### Claim 14 (depends on 1) The method for controlling the memory device according to claim 1, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, applying a third voltage to the first source line, the first voltage is lower than the third voltage, a timing of applying the third voltage is earlier than a timing of applying the first voltage, and the timing of applying the third voltage is earlier than a timing of applying the second voltage. ### Claim 15 (depends on 1) The method for controlling the memory device according to claim 1, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, applying a third voltage to the first source line, and a timing of applying the third voltage is earlier than a timing of applying the first voltage. ### Claim 16 (depends on 1) The method for controlling the memory device according to claim 1, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, applying a third voltage to the first source line, a timing of applying the third voltage is earlier than a timing of applying the first voltage, and the timing of applying the third voltage is earlier than a timing of applying the second voltage. ### Claim 17 (depends on 1) The method for controlling the memory device according to claim 1, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, applying a third voltage to the first source line, applying a fourth voltage to one of the first word lines, applying a fifth voltage to one of the second word lines, the first voltage is lower than the third voltage, and the fourth voltage is lower than the first voltage. ### Claim 18 (depends on 1) The method for controlling the memory device according to claim 1, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, applying a third voltage to the first source line, applying a fourth voltage to one of the first word lines, applying a fifth voltage to one of the second word lines, the first voltage is lower than the third voltage, the fourth voltage is lower than the second voltage, and a difference between the first voltage and the second voltage is smaller than a difference between the second voltage and the fourth voltage. ### Claim 19 (depends on 1) The method for controlling the memory device according to claim 1, further comprising a plurality of first dummy word lines connected between the first drain side selective transistor and the first source side selective transistor, a plurality of second dummy word lines connected between the second drain side selective transistor and the second source side selective transistor, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, applying a third voltage to the first source line, applying a fourth voltage to one of the first word lines, applying a fifth voltage to one of the second word lines, applying a sixth voltage to one of the first dummy word lines, applying a seventh voltage to one of the second dummy word lines, the first voltage is lower than the third voltage, the sixth voltage is lower than the first voltage, and the fourth voltage is lower than the sixth voltage. ### Claim 20 (depends on 1) The method for controlling the memory device according to claim 1, further comprising a plurality of first dummy word lines connected between the first drain side selective transistor and the first source side selective transistor, a plurality of second dummy word lines connected between the second drain side selective transistor and the second source side selective transistor, wherein the erase operation includes applying a first voltage to the first source side select gate line, applying a second voltage to the second source side select gate line, applying a third voltage to the first source line, applying a fourth voltage to one of the first word lines, applying a fifth voltage to one of the second word lines, applying a sixth voltage to one of the first dummy word lines, applying a seventh voltage to one of the second dummy word lines, the first voltage is lower than the third voltage, the sixth voltage is lower than the first voltage, the fourth voltage is lower than the sixth voltage, a timing of applying the third voltage is earlier than a timing of applying the first voltage, and the timing of applying the third voltage is earlier than a timing of applying the second voltage. ### Claim 21 (depends on 20) The method for controlling the memory device according to claim 20, wherein a distance between a gate of the first drain side selective transistor and one of the nearest gates of the first memory cells is longer than a distance between the gates of the first memory cells. ### Claim 22 (depends on 20) The method for controlling the memory device according to claim 20, wherein a distance between a gate of the first drain side selective transistor and one of the nearest gates of the first memory cells is doubled or more than a distance between the gates of the first memory cells. ### Claim 23 (depends on 20) The method for controlling the memory device according to claim 20, wherein a distance between the gate of the second source side selective transistor and one of the nearest gates of the second memory cells is longer than a distance between the gates of the second memory cells. ### Claim 24 (depends on 20) The method for controlling the memory device according to claim 20, wherein a distance between the gate of the second source side selective transistor and one of the nearest gates of the second memory cells is doubled or more than a distance between the gates of the second memory cells. ### Claim 25 (depends on 20) The method for controlling the memory device according to claim 20, further comprising a plurality of third memory cells, a first joining portion joining the first memory cells and the third memory cells in series, a plurality of fourth memory cells, a second joining portion joining the second memory cells and the fourth memory cells in series, wherein the first joining portion and the second joining portion, include poly silicon. ### Claim 26 (depends on 1) The method for controlling the memory device according to claim 1, further comprising: a plurality of third memory cells connected between the first drain side selective transistor and the first source side selective transistor; a plurality of fourth memory cells connected between the second drain side selective transistor and the second source side selective transistor; a plurality of third word lines connected to gates of the third memory cells; and a plurality of fourth word lines connected to gates of the fourth memory cells, the plurality of first control gate lines being connected to the plurality of fourth word lines not via any of the plurality of the second word lines or any of the plurality of the third word lines, and the plurality of second control gate lines being connected to the plurality of third word lines not via any of the plurality of the first word lines or any of the plurality of the fourth word lines.