# US 11,908,523 B2 · Express programming using advanced cache register release in a memory sub-system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,523 B2 - Document ID: US11908523B2 - Status: Granted - Kind: B2 - Application number: 17/675,526 - Filed: 2022-02-18 - Published: 2023-03-02 - Granted: 2024-02-20 - Earliest claimed: 2021-09-01 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Walter Di Francesco; Violante Moschiano; Umberto Siciliani - Web page: https://patentgrep.com/patent/US11908523B2 ## CPC - G11C 16/10: Programming or data input circuits - G06F 12/0215: {with look ahead addressing means} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G06F 2212/1016: Performance improvement - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/60: Details of cache memory - G06F 2212/72: Details relating to flash memory management - G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks - G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency - G11C 16/32: Timing circuits - G11C 2211/5643: Multilevel memory comprising cache storage devices - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition. ## Claims ### Claim 1 A memory device comprising: a memory array comprising a set of memory cells configured as a multi-level cell (MLC) memory; and control logic, operatively coupled with the memory array, to perform operations comprising: initiating an express programming operation to program the set of memory cells to a target programming level of a set of programming levels; storing, in a cache register, a set of data associated with the express programming operation; at a first time during execution of the express programming operation, executing a prediction operation to determine a prediction result corresponding to a programming status of the set of memory cells; comparing the prediction result to a threshold level to determine whether a condition is satisfied; and causing a release of the set of data associated with the express programming operation from the cache register in response to the condition being satisfied. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the prediction result represents a predicted quantity of the set of memory cells associated with an established programming status. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the condition is satisfied if the predicted quantity of the prediction result is greater than or equal to the threshold level. ### Claim 4 (depends on 1) The memory device of claim 1, the operations further comprising updating a signal associated with the cache register from a busy status to a ready status in response to the condition being satisfied. ### Claim 5 (depends on 4) The memory device of claim 4, the operations further comprising in view of the ready status, loading, into the cache register, a next set of data associated with a next express programming operation being applied to the memory array. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the set of data is released from the cache register at a time prior to completion of the express programming operation. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the set of data is released from the cache register at a time prior to one or more programming pulses and a voltage discharge phase associated with the express programming operation being applied to the memory array. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the set of data is released from the cache register at a time prior to one or more programming loops, a final programming pulse and a voltage discharge phase associated with the express programming operation. ### Claim 9 (depends on 8) The memory device of claim 8, the operations further comprising initiating execution of a next express programming operation based on a next set of data stored in the cache register prior to completion of the express programming operation. ### Claim 10 A method comprising: initiating a first express programming operation to program a set of memory cells of a memory array of a memory device to a target programming level of a set of programming levels; storing, in a cache register, a first set of data associated with the first express programming operation; at one or more checkpoints during execution of the first express programming operation, executing, by a processing device, a prediction operation to determine a prediction result corresponding to a programming status of the set of memory cells; comparing the prediction result to a threshold level to determine whether a condition is satisfied; causing a release of the first set of data associated with the first express programming operation from the cache register in response to the condition being satisfied; and loading, into the cache register, a second set of data associated with a second express programming operation to be applied to the memory array. ### Claim 11 (depends on 10) The method of claim 10, further comprising updating a signal associated with the cache register from a busy status to a ready status in response to the condition being satisfied. ### Claim 12 (depends on 10) The method of claim 10, wherein the second set of data is loaded into the cache register prior to completion of the first express programming operation. ### Claim 13 (depends on 10) The method of claim 10, wherein the first set of data is released from the cache register prior to completion of the first express programming operation. ### Claim 14 (depends on 10) The method of claim 10, wherein the one or more checkpoints associated with the executing of the prediction operation are established following one or more programming loops of the first express programming operation, where each of the one or more programming loops comprises application of a programming pulse and execution of a program verify operation. ### Claim 15 (depends on 10) The method of claim 10, wherein the prediction operation is performed following a programming loop, and wherein the prediction result comprises a predicted quantity of the set of memory cells for which the programming status is known following a next programming loop. ### Claim 16 A memory device comprising: a memory array comprising a set of memory cells; and control logic, operatively coupled with the memory array, to perform operations comprising: initiating a first express programming operation to program the set of memory cells to a target programming level of a set of programming levels; storing, in a cache register, a first set of data associated with the first express programming operation; at one or more checkpoints during execution of the first express programming operation, executing a prediction operation to determine a prediction result corresponding to a programming status of the set of memory cells; comparing the prediction result to a threshold level to determine whether a condition is satisfied; causing a release of the first set of data associated with the first express programming operation from the cache register in response to the condition being satisfied; and loading, into the cache register, a second set of data associated with a second express programming operation to be applied to the memory array. ### Claim 17 (depends on 16) The memory device of claim 16, wherein the second set of data is loaded into the cache register prior to completion of the first express programming operation. ### Claim 18 (depends on 16) The memory device of claim 16, wherein the release of the cache register is caused prior to completion of the first express programming operation. ### Claim 19 (depends on 16) The memory device of claim 16, wherein the one or more checkpoints associated with the executing of the prediction operation are established following one or more programming loops of the first express programming operation, wherein each of the one or more programming loops comprises application of a programming pulse and execution of a program verify operation. ### Claim 20 (depends on 16) The memory device of claim 16, wherein the prediction operation is performed following a programming loop, and wherein the prediction result comprises a predicted quantity of the set of memory cells for which the programming status is known following a next programming loop.