# US 11,908,520 B2 · Memory device

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- Number: US 11,908,520 B2
- Document ID: US11908520B2
- Status: Granted
- Kind: B2
- Application number: 17/459,420
- Filed: 2021-08-27
- Published: 2022-08-04
- Granted: 2024-02-20
- Earliest claimed: 2021-02-03
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Hideto Takekida
- Web page: https://patentgrep.com/patent/US11908520B2

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

According to one embodiment, a memory device includes a first chip and a second chip provided over the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode.

## Claims

### Claim 1

A memory device comprising:
a first chip; and
a second chip bonded to the first chip,
wherein the first chip includes a first substrate, a first circuit provided on the first substrate, a first electrode facing a bonding surface of the first chip and the second chip with the first electrode electrically connected to the first circuit, and a first memory cell array provided between the first substrate and the first electrode and electrically connected to the first circuit, and
the second chip includes a second substrate, a second circuit provided on the second substrate, a second electrode facing the bonding surface with the second electrode electrically connected to the second circuit and being in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode with the second memory cell array electrically connected to the second circuit.

### Claim 2 (depends on 1)

The memory device according to claim 1,
wherein the first memory cell array includes
a first conductor layer,
a first semiconductor film extending in the first conductor layer along a first direction, and
a first charge storage film provided between the first conductor layer and the first semiconductor film,
the second memory cell array includes
a second conductor layer,
a second semiconductor film extending in the second conductor layer along the first direction, and
a second charge storage film provided between the second conductor layer and the second semiconductor film,
wherein the first direction intersects a facing between the first substrate and the second substrate.

### Claim 3 (depends on 2)

The memory device according to claim 2,
wherein the first chip includes a first row decoder configured to be electrically connected to the first conductor layer, and
the second chip includes a second row decoder configured to be electrically connected to the second conductor layer.

### Claim 4 (depends on 3)

The memory device according to claim 3,
wherein, along the first direction, a thickness of the first substrate is equal to a thickness of the second substrate.

### Claim 5 (depends on 2)

The memory device according to claim 2,
wherein the first chip includes a first row decoder configured to be electrically connected to the first conductor layer, and a second row decoder configured to be electrically connected to the second conductor layer.

### Claim 6 (depends on 5)

The memory device according to claim 5,
wherein, along the first direction, a thickness of the first substrate is greater than a thickness of the second substrate.

### Claim 7 (depends on 1)

The memory device according to claim 1,
wherein the second substrate has a first surface facing the first substrate and a second surface located on an opposite side of the second substrate, and
the second chip includes a pad provided on the second surface.

### Claim 8 (depends on 1)

The memory device according to claim 1,
wherein the first chip includes
a first sub-chip including the first substrate, and
a second sub-chip provided on the first sub-chip and including the first memory cell array and the first electrode.

### Claim 9 (depends on 8)

The memory device according to claim 8,
wherein the second chip includes
a third sub-chip provided on the second sub-chip and including the second memory cell array and the second electrode, and
a fourth sub-chip provided on the third sub-chip and including the second substrate.

### Claim 10 (depends on 1)

The memory device according to claim 1,
wherein the first chip includes
a first sub-chip including the first substrate,
a second sub-chip provided above the first sub-chip and including the first memory cell array and the first electrode, and
a fifth sub-chip provided between the first sub-chip and the second sub-chip and including a third memory cell array.

### Claim 11 (depends on 1)

The memory device according to claim 1,
wherein the first electrode and the second electrode include copper.

### Claim 12 (depends on 7)

The memory device according to claim 7,
wherein the pad includes aluminum.

### Claim 13 (depends on 1)

The memory device according to claim 1,
wherein the first chip includes one or more first insulator layers through which the first electrode extends, and wherein the second chip includes one or more second insulator layers through which the second electrode extends.

### Claim 14 (depends on 13)

The memory device according to claim 13,
wherein one of the first insulator layers is in contact with one of the second insulator layers.

### Claim 15

A method, comprising:
providing a first chip including a first substrate, a first circuit provided on the first substrate, a first electrode, and a first memory cell array;
providing a second chip including a second substrate, a second circuit provided on the second substrate, a second electrode, and a second memory cell array; and
bonding the first chip to the second chip through the first and second electrodes, such that the one or more first decoders are coupled to the first memory cell array, the first electrode faces a bonding surface of the first chip and the second chip with the first electrode electrically connected to the first circuit, the first memory cell array is provided between the first substrate and the first electrode and electrically connected to the first circuit, the second electrode faces the bonding surface with the second electrode electrically connected to the second circuit and being in contact with the first electrode, and the second memory cell array is provided between the second substrate and the second electrode and electrically connected to the second circuit.

### Claim 16 (depends on 15)

The method of claim 15, wherein a thickness of the first substrate is equal to a thickness of the second substrate.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first circuit and the second circuit each include a decoder.