# US 11,908,519 B2 · Pre-compare operation for compact low-leakage dual-compare cam cell > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,519 B2 - Document ID: US11908519B2 - Status: Granted - Kind: B2 - Application number: 17/462,659 - Filed: 2021-08-31 - Published: 2023-03-02 - Granted: 2024-02-20 - Earliest claimed: 2021-08-31 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Hema Ramamurthy; Michael Lee - Web page: https://patentgrep.com/patent/US11908519B2 ## CPC - G11C 15/04: using semiconductor elements - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Pre-comparing data in a dual compare content compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. A first compare input and a second compare input of a column in a dual compare content addressable memory (“CAM”) device. A pre-compare signal is generated based on comparing the first compare input and the second compare input. A first polarity of the first compare input is compared with a first polarity a storage node data. A compare output of the first compare input is generated based on a logic state of the pre-compare signal. A first compare match is generated based on the compare output and a second compare match is generated based on the pre-compare signal. ## Claims ### Claim 1 A method for pre-comparing data in a dual compare content addressable memory (“CAM”) device having one or more comparators, comprising: comparing a first compare input and a second compare input of a column in a dual compare content addressable memory (“CAM”) device; generating a pre-compare signal based on comparing the first compare input and the second compare input; comparing a first polarity of the first compare input with a first polarity of a storage node data; generating a compare output of the first compare input based on a logic state of the pre-compare signal; and generating a first compare match based on the compare output and a second compare match based on the pre-compare signal. ### Claim 2 (depends on 1) The method of claim 1, wherein comparing the first compare input and the second compare input of a column in a dual CAM device further includes determining the first compare input and a second compare input have similar logic states. ### Claim 3 (depends on 1) The method of claim 1, wherein generating the compare output of the first compare input based on the logic state of the pre-compare signal further includes determining the first compare input and the second compare input have dissimilar logic states. ### Claim 4 (depends on 1) The method of claim 1, wherein generating the compare output of the first compare input based on the logic state of the pre-compare signal further includes determining a logic state of the compare output based on comparing the first polarity of the first compare input with the first polarity of a storage node data. ### Claim 5 (depends on 1) The method of claim 1, wherein generating the compare output of the first compare input based on the logic state of the pre-compare signal further includes setting a logic state of the compare output as a first logic state based on comparing the first polarity of the first compare input with the first polarity of a storage node data. ### Claim 6 (depends on 1) The method of claim 1, wherein generating the compare output of the first compare input based on the logic state of the pre-compare signal further includes setting a logic state of the compare output as a second logic state based on comparing the first polarity of the first compare input with a first polarity of a storage node data. ### Claim 7 (depends on 1) The method of claim 1, wherein generating a first compare match based on the compare output and a second compare match based on the pre-compare signal further includes generating the first compare match by combining the compare output from each bit in a row of the dual compare CAM device and generating the second compare match by combining the pre-compare signal from each bit in a row of the dual compare CAM device. ### Claim 8 A system for pre-comparing data in a compare content addressable memory (“CAM”) device having one or more comparators in a computing environment, comprising one or more computers with executable instructions that when executing cause the system to: compare a first compare input and a second compare input of a column in a compare content addressable memory (“CAM”) device; generate a pre-compare signal based on comparing the first compare input and the second compare input; compare a first polarity of the first compare input with a first polarity of a storage node data; generate a compare output of the first compare input based on a logic state of the pre-compare signal; and generate a first compare match based on the compare output and a second compare match based on the pre-compare signal. ### Claim 9 (depends on 8) The system of claim 8, wherein the executable instructions when executed cause the system to determine the first compare input and a second compare input have similar logic states, wherein the CAM devices is a dual-bit CAM device or a multi-bit CAM device. ### Claim 10 (depends on 8) The system of claim 8, wherein the executable instructions when executed cause the system to determine the first compare input and the second compare input have dissimilar logic states. ### Claim 11 (depends on 8) The system of claim 8, wherein the executable instructions when executed cause the system to determine a logic state of the compare output based on comparing the first polarity of the first compare input with the first polarity of a storage node data. ### Claim 12 (depends on 8) The system of claim 8, wherein the executable instructions when executed cause the system to set a logic state of the compare output as a first logic state based on comparing the first polarity of the first compare input with the first polarity of a storage node data. ### Claim 13 (depends on 8) The system of claim 8, wherein the executable instructions when executed cause the system to set a logic state of the compare output as a second logic state based on comparing the first polarity of the first compare input with a first polarity of a storage node data. ### Claim 14 (depends on 8) The system of claim 8, wherein generating a first compare match based on the compare output and a second compare match based on the pre-compare signal further includes generating the first compare match by combining the compare output from each bit in a row of the compare CAM device and generating the second compare match by combining the pre-compare signal from each bit in a row of the compare CAM device. ### Claim 15 A computer program product for pre-comparing data in a dual compare content addressable memory (“CAM”) device having one or more comparators in a computing environment, the computer program product comprising one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instruction comprising: program instructions to compare a first compare input and a second compare input of a column in a dual compare content addressable memory (“CAM”) device; program instructions to generate a pre-compare signal based on comparing the first compare input and the second compare input; program instructions to compare a first polarity of the first compare input with a first polarity of a storage node data; program instructions to generate a compare output of the first compare input based on a logic state of the pre-compare signal; and program instructions to generate a first compare match based on the compare output and a second compare match based on the pre-compare signal. ### Claim 16 (depends on 15) The computer program product of claim 15, further including program instructions to determine the first compare input and a second compare input have similar logic states. ### Claim 17 (depends on 15) The computer program product of claim 15, further including program instructions to determine the first compare input and the second compare input have dissimilar logic states. ### Claim 18 (depends on 15) The computer program product of claim 15, further including program instructions to determine a logic state of the compare output based on comparing the first polarity of the first compare input with the first polarity of a storage node data. ### Claim 19 (depends on 15) The computer program product of claim 15, further including program instructions to set a logic state of the compare output as a first logic state or second logic state based on comparing the first polarity of the first compare input with the first polarity of a storage node data. ### Claim 20 (depends on 15) The computer program product of claim 15, wherein generating a first compare match based on the compare output and a second compare match based on the pre-compare signal further includes generating the first compare match by combining the compare output from each bit in a row of the dual compare CAM device and generating the second compare match by combining the pre-compare signal from each bit in a row of the dual compare CAM device.