# US 11,908,516 B2 · Resistive memory apparatus and operating method thereof and memory cell array thereof

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- Number: US 11,908,516 B2
- Document ID: US11908516B2
- Status: Granted
- Kind: B2
- Application number: 17/458,559
- Filed: 2021-08-27
- Published: 2022-03-03
- Granted: 2024-02-20
- Earliest claimed: 2020-08-27
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Ming-Che Lin; Min-Chih Wei; Ping-Kun Wang; Yu-Ting Chen; Chih-Cheng Fu; Chang-Tsung Pai
- Web page: https://patentgrep.com/patent/US11908516B2

## CPC

- G11C 13/0038: {Power supply circuits}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2013/0083: {Write to perform initialising, forming process, electro forming or conditioning}
- G11C 2213/51: Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode
- G11C 2213/56: Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
- G11C 2213/79: Array wherein the access device being a transistor
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

## Claims

### Claim 1

A resistive memory apparatus, comprising:
a memory cell array, comprising a plurality of memory cells, each of the memory cells comprising a resistive switching element;
at least one dummy transistor, electrically isolated from the resistive switching element; and
a control circuit, coupled to the memory cell array and the at least one dummy transistor, and configured to provide a first bit line voltage, a source line voltage and a word line voltage to the at least one dummy transistor so that the at least one dummy transistor outputs a saturation current and determine a value of a second bit line voltage for driving the memory cells according to the saturation current,
wherein the control circuit is configured to determine which one of a plurality of saturation current intervals the saturation current of the at least one dummy transistor is in, and drive the memory cells according to the second bit line voltage corresponding to the saturation current interval.

### Claim 2 (depends on 1)

The resistive memory apparatus of claim 1, wherein the control circuit is configured to drive the memory cells according to the determined second bit line voltage so that a cell current of the memory cells is greater than a target current value.

### Claim 3 (depends on 1)

The resistive memory apparatus of claim 1, wherein the resistive switching element comprises a plurality of regions with different conduction conditions, and the second bit line voltage is configured to drive at least one of the regions with the different conduction conditions to be turned on.

### Claim 4 (depends on 3)

The resistive memory apparatus of claim 3, wherein the resistive switching element comprises a bottom electrode layer, a resistive switching layer, a first barrier layer, an oxygen ion reservoir layer, a second barrier layer and a top electrode layer, the resistive switching layer is disposed between the first barrier layer and the bottom electrode layer, the oxygen ion reservoir layer is disposed on the first barrier layer, and the top electrode layer is disposed on the second barrier layer.

### Claim 5 (depends on 3)

The resistive memory apparatus of claim 3, wherein the regions with the different conduction conditions have different doping concentrations.

### Claim 6 (depends on 3)

The resistive memory apparatus of claim 3, wherein the second bit line voltage decreases as the saturation current increases.

### Claim 7 (depends on 1)

The resistive memory apparatus of claim 1, further comprising:
a sense circuit, coupled to the control circuit and the at least one dummy transistor, and configured to sense the saturation current of the at least one dummy transistor and output the saturation current to the control circuit; and
a voltage generating circuit, coupled to the control circuit and the memory cell array, and configured to generate and output the second bit line voltage to the memory cell array.

### Claim 8 (depends on 1)

The resistive memory apparatus of claim 1, wherein the control circuit determines the value of the second bit line voltage according a lookup table; and generates and outputs the second bit line voltage according to the determined value of the second bit line voltage.

### Claim 9 (depends on 8)

The resistive memory apparatus of claim 8, wherein the lookup table comprises the plurality of saturation current intervals and a relationship of the second bit line voltage corresponding to each of the saturation current intervals.

### Claim 10 (depends on 8)

The resistive memory apparatus of claim 8, wherein the lookup table is stored through a plurality of control bits.

### Claim 11 (depends on 5)

The resistive memory apparatus of claim 5, wherein a number of the regions with the different conduction conditions being turned on increases as the bit line voltage increases.

### Claim 12 (depends on 11)

The resistive memory apparatus of claim 11, wherein the doping concentrations of the regions with the different conduction conditions being turned on is greater as the bit line voltage decreases.

### Claim 13 (depends on 1)

The resistive memory apparatus of claim 1, wherein resistive memory apparatus comprises a plurality of dummy transistors arranged in a column to form a dummy transistor column.

### Claim 14 (depends on 13)

The resistive memory apparatus of claim 13, wherein the dummy transistor column and the memory cells are arranged in an array.

### Claim 15 (depends on 4)

The resistive memory apparatus of claim 4, wherein the resistive switching layer comprises a plurality of regions having different doping concentrations.

### Claim 16 (depends on 15)

The resistive memory apparatus of claim 15, wherein the resistive switching layer comprises four regions having the different doping concentrations, and the four regions are formed by using one or two masks.