# US 11,908,515 B2 · 2T-1R architecture for resistive ram > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,515 B2 - Document ID: US11908515B2 - Status: Granted - Kind: B2 - Application number: 18/098,548 - Filed: 2023-01-18 - Published: 2023-05-18 - Granted: 2024-02-20 - Earliest claimed: 2013-12-06 - Assignees: Hefei Reliance Memory Limited - Applicants: Hefei Reliance Memory Limited - Inventors: Deepak Chandra Sekar; Wayne Frederick Ellis; Brent Steven Haukness; Gary Bela Bronner; Thomas Vogelsang - Web page: https://patentgrep.com/patent/US11908515B2 ## CPC - G11C 13/0028: {Word-line or row circuits} - G11C 7/08: Control thereof - G11C 8/10: Decoders - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 13/0023: {Address circuits or decoders} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/003: {Cell access} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 13/0097: {Erasing, e.g. resetting, circuits or methods} - G11C 2013/0071: {Write using write potential applied to access device gate} - G11C 2013/0083: {Write to perform initialising, forming process, electro forming or conditioning} - G11C 2013/0088: {Write with the simultaneous writing of a plurality of cells} - G11C 2213/74: Array wherein each memory cell has more than one access device - G11C 2213/79: Array wherein the access device being a transistor - G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground. ## Claims ### Claim 1 An apparatus comprising: multiple memory cells each comprising two transistors and a resistive memory element, wherein: a first transistor of a first memory cell is electrically coupled to a first transistor of a second memory cell and a source line; a first transistor of a third memory cell is electrically coupled to a first transistor of a fourth memory cell and the source line; the resistive memory element of the first memory cell is coupled to the resistive memory element of the second memory cell and a first bit line; the resistive memory element of the third memory cell is coupled to the resistive memory element of the fourth memory cell and a second bit line; a first word line is electrically coupled to a second transistor of the first memory cell and a second transistor of the third memory cell, wherein the second transistor of the first memory cell is coupled between the first transistor of the first memory cell and the resistive element of the first memory cell; a second word line is electrically coupled to a second transistor of the second memory cell and a second transistor of the fourth memory cell; a third word line is electrically coupled to the first transistor of the first memory cell and the first transistor of the third memory cell; and a fourth word line is electrically coupled to the first transistor of the second memory cell and the first transistor of the fourth memory cell. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising: a row driver circuit configured to drive the first bit line, the second bit line, the first word line, the second word line, and the source line. ### Claim 3 (depends on 1) The apparatus of claim 1, further comprising: a row driver circuit configured to apply a voltage to the first word line and the third word line during a form or set operation of the first and third memory cells. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the row driver circuit comprises: a current mirror configured to apply a voltage to the first word line and the third word line during a form or set operation of the first and third memory cells. ### Claim 5 (depends on 1) The apparatus of claim 1, further comprising: a row driver circuit current mirror configured to apply a voltage to the second word line and the fourth word line during a form or set operation of the second and fourth memory cells. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the row driver circuit comprises: a current mirror configured to apply a voltage to the second word line and the fourth word line during a form or set operation of the second and fourth memory cells. ### Claim 7 (depends on 1) The apparatus of claim 1, further comprising: a row driver circuit configured to apply a first voltage to the first word line and the third word line, and to apply a second voltage to the source line, during a reset operation of the first and third memory cells. ### Claim 8 (depends on 1) The apparatus of claim 1, further comprising: a row driver circuit configured to apply a first voltage to the second word line and the fourth word line, and to apply a second voltage to the source line, during a reset operation of the second and fourth memory cells. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein: the source line is electrically coupled to a source of the first transistor of each of the first, second, third, and fourth memory cells. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein: the first word line is electrically coupled to a gate of the second transistor of the first memory cell and a gate of the second transistor of the third memory cell; the second word line is electrically coupled to a gate of the second transistor of the second memory cell and a gate of the second transistor of the fourth memory cell; the third word line is electrically coupled to a gate of the first transistor of the first memory cell and a gate of the first transistor of the third memory cell; and the fourth word line is electrically coupled to a gate of the first transistor of the second memory cell and a gate of the first transistor of the fourth memory cell. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein: a drain of the first transistor of the first memory cell is electrically coupled to a source of the second transistor of the first memory cell; a drain of the first transistor of the second memory cell is electrically coupled to a source of the second transistor of the second memory cell; a drain of the first transistor of the third memory cell is electrically coupled to a source of the second transistor of the third memory cell; and a drain of the first transistor of the fourth memory cell is electrically coupled to a source of the second transistor of the fourth memory cell. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein: the resistive memory element of the first memory cell is coupled to the drain of the second transistor of the first memory cell; the resistive memory element of the second memory cell is coupled to the drain of the second transistor of the second memory cell; the resistive memory element of the third memory cell is coupled to the drain of the second transistor of the third memory cell; and the resistive memory element of the fourth memory cell is coupled to the drain of the second transistor of the fourth memory cell. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the multiple memory cells further comprise fifth, sixth, seventh, and eighth memory cells, and wherein: the source line is a first source line; a first transistor of the fifth memory cell is electrically coupled to a first transistor of the sixth memory cell and a second source line; a first transistor of the seventh memory cell is electrically coupled to a first transistor of the eight memory cell and the second source line; the resistive memory element of the fifth memory cell is coupled to the resistive memory element of the sixth memory cell and a third bit line; the resistive memory element of the seventh memory cell is coupled to the resistive memory element of the eighth memory cell and a fourth bit line; the first word line is electrically coupled to a second transistor of the fifth memory cell and a second transistor of the seventh memory cell; the second word line is electrically coupled to a second transistor of the sixth memory cell and a second transistor of the eighth memory cell; the third word line is electrically coupled to the first transistor of the fifth memory cell and the first transistor of the seventh memory cell; and the fourth word line is electrically coupled to the first transistor of the sixth memory cell and the first transistor of the eighth memory cell. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein: the second source line is electrically coupled to a source of the first transistor. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein: the first word line is electrically coupled to a gate of the second transistor of the fifth memory cell and a gate of the second transistor of the seventh memory cell; the second word line is electrically coupled to a gate of the second transistor of the sixth memory cell and a gate of the second transistor of the eighth memory cell; the third word line is electrically coupled to a gate of the first transistor of the fifth memory cell and a gate of the first transistor of the seventh memory cell; and the fourth word line is electrically coupled to a gate of the first transistor of the sixth memory cell and a gate of the first transistor of the eighth memory cell. ### Claim 16 (depends on 13) The apparatus of claim 13, wherein: a drain of the first transistor of the fifth memory cell is electrically coupled to a source of the second transistor of the fifth memory cell; a drain of the first transistor of the sixth memory cell is electrically coupled to a source of the second transistor of the sixth memory cell; a drain of the first transistor of the seventh memory cell is electrically coupled to a source of the second transistor of the seventh memory cell; and a drain of the first transistor of the eighth memory cell is electrically coupled to a source of the second transistor of the eighth memory cell. ### Claim 17 (depends on 13) The apparatus of claim 13, wherein: the resistive memory element of the fifth memory cell is coupled to the drain of the second transistor of the fifth memory cell; the resistive memory element of the sixth memory cell is coupled to the drain of the second transistor of the sixth memory cell; the resistive memory element of the seventh memory cell is coupled to the drain of the second transistor of the seventh memory cell; and the resistive memory element of the eighth memory cell is coupled to the drain of the second transistor of the eighth memory cell. ### Claim 18 An apparatus comprising: multiple memory cells each comprising two transistors and a resistive memory element, wherein: a first transistor of a first memory cell is electrically coupled to a first transistor of a second memory cell and a source line, a first transistor of a third memory cell is electrically coupled to a first transistor of a fourth memory cell and the source line, the resistive memory element of the first memory cell is coupled to the resistive memory element of the second memory cell and a first bit line, the resistive memory element of the third memory cell is coupled to the resistive memory element of the fourth memory cell and a second bit line, a first word line is electrically coupled to a second transistor of the first memory cell and a second transistor of the third memory cell, a second word line is electrically coupled to a second transistor of the second memory cell and a second transistor of the fourth memory cell, a third word line is electrically coupled to the first transistor of the first memory cell and the first transistor of the third memory cell, and a fourth word line is electrically coupled to the first transistor of the second memory cell and the first transistor of the fourth memory cell; and a row driver circuit configured to apply a voltage to the first word line and the third word line during a form or set operation of the first and third memory cells, wherein the row driver circuit comprises a current mirror configured to apply a voltage to the first word line and the third word line during a form or set operation of the first and third memory cells. ### Claim 19 An apparatus comprising: multiple memory cells each comprising two transistors and a resistive memory element, wherein: a first transistor of a first memory cell is electrically coupled to a first transistor of a second memory cell and a source line, a first transistor of a third memory cell is electrically coupled to a first transistor of a fourth memory cell and the source line, the resistive memory element of the first memory cell is coupled to the resistive memory element of the second memory cell and a first bit line, the resistive memory element of the third memory cell is coupled to the resistive memory element of the fourth memory cell and a second bit line, a first word line is electrically coupled to a second transistor of the first memory cell and a second transistor of the third memory cell, a second word line is electrically coupled to a second transistor of the second memory cell and a second transistor of the fourth memory cell, a third word line is electrically coupled to the first transistor of the first memory cell and the first transistor of the third memory cell, and a fourth word line is electrically coupled to the first transistor of the second memory cell and the first transistor of the fourth memory cell; and a row driver circuit current mirror configured to apply a voltage to the second word line and the fourth word line during a form or set operation of the second and fourth memory cells.