# US 11,908,513 B2 · Neural memory array storing synapsis weights in differential cell pairs

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,908,513 B2
- Document ID: US11908513B2
- Status: Granted
- Kind: B2
- Application number: 18/103,383
- Filed: 2023-01-30
- Published: 2023-06-08
- Granted: 2024-02-20
- Earliest claimed: 2020-03-05
- Assignees: Silicon Storage Technology, Inc.
- Applicants: Silicon Storage Technology, Inc.
- Inventors: Hieu Van Tran; Thuan Vu; Stephen Trinh; Stanley Hong; Anh Ly; Vipin Tiwari
- Web page: https://patentgrep.com/patent/US11908513B2

## CPC

- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G06N 3/045: Combinations of networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/063: using electronic means
- G06N 3/065: Analogue means
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/0425: {comprising cells containing a merged floating gate and select transistor}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- H03F 3/005: {using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence)}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03M 1/007: {among different resolutions}
- H03M 1/145: {the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence)}
- H03M 1/164: {the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence)}
- H03M 1/466: {using switched capacitors}
- G06N 3/048: Activation functions
- H03F 2203/45526: the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
- H03F 2203/45536: the FBC comprising a switch and being coupled between the LC and the IC
- H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14)
- H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array}
- H03M 1/56: Input signal compared with linear ramp
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H03F: AMPLIFIERS
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).

## Claims

### Claim 1

A system comprising:
a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and
a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column;
wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).

### Claim 2 (depends on 1)

The system of claim 1, further comprising source line pulldown bit lines.

### Claim 3 (depends on 1)

The system of claim 1, further comprising redundant columns.

### Claim 4 (depends on 3)

The system of claim 3, wherein the redundant columns are used to remap weights from a W+ or W− column.

### Claim 5 (depends on 4)

The system of claim 4, wherein the redundant columns are used to remap weights to avoid floating gate to floating gate coupling.

### Claim 6 (depends on 4)

The system of claim 4, wherein the redundant columns are used to remap weights to distribute power more evenly among the columns.

### Claim 7 (depends on 4)

The system of claim 4, wherein the redundant columns are used to remap weight from noisy or defective cells.

### Claim 8 (depends on 1)

The system of claim 1, wherein the non-volatile memory cells in the first array and the second array are split gate flash memory cells.

### Claim 9 (depends on 1)

The system of claim 1, wherein the non-volatile memory cells in the first array and the second array are stacked gate flash memory cells.

### Claim 10 (depends on 1)

The system of claim 1, further comprising a summer for summing outputs from one or more bit lines.

### Claim 11 (depends on 10)

The system of claim 10, wherein the summer is adjustable based on a variable resistor.

### Claim 12 (depends on 10)

The system of claim 10, wherein the summer is adjustable based on a variable capacitor.

### Claim 13 (depends on 10)

The system of claim 10, wherein the summer comprises a switched capacitor circuit and an operational amplifier.

### Claim 14 (depends on 10)

The system of claim 10, further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.

### Claim 15 (depends on 14)

The system of claim 14, wherein the analog-to-digital converter comprises a successive approximation register.

### Claim 16 (depends on 14)

The system of claim 14, wherein the analog-to-digital converter is a pipelined analog-to-digital converter.