# US 11,908,512 B2 · 3D NAND flash memory devices and related electronic systems

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- Number: US 11,908,512 B2
- Document ID: US11908512B2
- Status: Granted
- Kind: B2
- Application number: 18/148,684
- Filed: 2022-12-30
- Published: 2023-05-11
- Granted: 2024-02-20
- Earliest claimed: 2021-08-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Tomoharu Tanaka; Yoshiaki Fukuzumi
- Web page: https://patentgrep.com/patent/US11908512B2

## CPC

- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 16/24: Bit-line control circuits
- B81B 7/008: {MEMS characterised by an electronic circuit specially adapted for controlling or driving the same (B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00)}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/40: characterised by the peripheral circuit region
- B81B 2201/07: Data storage devices, static or dynamic memories
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

## Claims

### Claim 1

A 3D NAND Flash memory device, comprising:
a stack structure comprising tiers each comprising conductive material and insulative material vertically neighboring the conductive material;
strings of memory cells vertically extending through the stack structure;
local bit lines vertically overlying and coupled to groups of the strings of memory cells;
global bit lines vertical overlying the local bit lines;
vertical sense transistors vertically interposed between the local bit lines and the global bit lines, the vertical sense transistors having gate electrodes coupled to the local bit lines;
vertical read transistors vertically interposed between and coupled to the vertical sense transistors and the global bit lines; and
vertical write transistors at a vertical elevation of the vertical read transistors, the vertical write transistors coupled to the local bit lines and the global bit lines.

### Claim 2 (depends on 1)

The 3D NAND Flash memory device of claim 1, further comprising source lines vertically interposed between the local bit lines and the vertical sense transistors and coupled to the vertical sense transistors.

### Claim 3 (depends on 2)

The 3D NAND Flash memory device of claim 2, wherein:
source regions of the vertical sense transistors are coupled to the source lines;
drain regions of the vertical sense transistors are coupled to source regions of the vertical read transistors; and
drain regions of the vertical read transistors are coupled to the global bit lines.

### Claim 4 (depends on 2)

The 3D NAND Flash memory device of claim 2, further comprising:
additional gate electrodes respectively shared by multiple of the vertical read transistors; and
further gate electrodes respectively shared by multiple of the vertical write transistors.

### Claim 5 (depends on 4)

The 3D NAND Flash memory device of claim 4, wherein:
the local bit lines, the global bit lines, and the gate electrodes extend in parallel with one another in a first horizontal direction; and
the source lines, the additional gate electrodes, and the further gate electrodes extend in parallel with one another in a second horizontal direction orthogonal to the first horizontal direction.

### Claim 6 (depends on 1)

The 3D NAND Flash memory device of claim 1, wherein:
a first of the local bit lines is coupled to a first group of the strings of memory cells, a first of the vertical sense transistors, and a first of the vertical write transistors; and
a first of the global bit lines is coupled to a first of the vertical read transistors and the first of the vertical write transistors.

### Claim 7 (depends on 6)

The 3D NAND Flash memory device of claim 6, wherein:
a second of the local bit lines is coupled to a second group of the strings of memory cells, a second of the vertical sense transistors, and a second of the vertical write transistors; and
a second of the global bit lines is coupled to a second of the vertical read transistors and the second of the vertical write transistors.

### Claim 8 (depends on 7)

The 3D NAND Flash memory device of claim 7, wherein:
the first of the vertical read transistors and the second of the vertical read transistors share a read gate electrode with one another; and
the first of the vertical write transistors and the second of the vertical write transistors share a write gate electrode with one another.

### Claim 9 (depends on 7)

The 3D NAND Flash memory device of claim 7, wherein:
the first of the vertical read transistors and the second of the vertical read transistors are operatively associated with different read gate electrodes than one another; and
the first of the vertical write transistors and the second of the vertical write transistors are operatively associated with different write gate electrodes than one another.

### Claim 10 (depends on 7)

The 3D NAND Flash memory device of claim 7, wherein:
the first of the vertical sense transistors and the first of the vertical read transistors share a first pillar structure with one another, the first pillar structure comprising semiconductor material and vertically extending from and between a source line and the first of the global bit lines; and
the second of the vertical sense transistors and the second of the vertical read transistors share a second pillar structure with one another, the second pillar structure comprising additional semiconductor material and vertically extending from and between the source line and the second of the global bit lines.

### Claim 11

A 3D NAND Flash memory device, comprising:
a stack structure comprising conductive structures and insulative structures vertically alternating with the conductive structures;
pillar structures vertically extending through the stack structure and individually comprising semiconductor material;
a local digit line overlying the stack structure and coupled to a group of the pillar structures;
a source line overlying the local digit line;
a vertical sense transistor overlying the source line, the vertical sense transistor coupled to the source line and the local digit line;
a vertical read transistor overlying the vertical sense transistor, the vertical read transistor substantially horizontally aligned with and coupled to the vertical sense transistor;
a vertical write transistor overlying the vertical sense transistor, the vertical write transistor coupled to the local digit line; and
a global digit line overlying and coupled to each of the vertical read transistor and the vertical write transistor.

### Claim 12 (depends on 11)

The 3D NAND Flash memory device of claim 11, wherein:
a gate electrode for the vertical sense transistor is coupled to the local digit line and horizontally extends in parallel with the local digit line in a first direction; and
additional gate electrodes for the vertical read transistor and the vertical write transistor horizontally extend in parallel with one another in a second direction orthogonal to the first direction.

### Claim 13 (depends on 12)

The 3D NAND Flash memory device of claim 12, wherein the vertical read transistor is substantially horizontally aligned with the vertical write transistor in the second direction.

### Claim 14 (depends on 13)

The 3D NAND Flash memory device of claim 13, wherein the vertical read transistor is substantially horizontally aligned with the vertical sense transistor in each of the first direction and the second direction.

### Claim 15 (depends on 11)

The 3D NAND Flash memory device of claim 11, wherein the vertical sense transistor and the vertical read transistor share an additional pillar structure with one another, the additional pillar structure comprising additional semiconductor material and vertically extending from the global digit line to the source line.

### Claim 16 (depends on 15)

The 3D NAND Flash memory device of claim 15, further comprising a further pillar structure operatively associated with the vertical write transistor, the further pillar structure comprising further semiconductor material and vertically extending from the global digit line to the local digit line.

### Claim 17 (depends on 16)

The 3D NAND Flash memory device of claim 16, wherein the additional pillar structure and the further pillar structure at least partially overlap one another in a first horizontal direction orthogonal to a second horizontal direction in which the local digit line and the global digit line each substantially linearly extend.

### Claim 18 (depends on 17)

The 3D NAND Flash memory device of claim 17, wherein the local digit line and the global digit line at least partially overlap one another in the first horizontal direction.

### Claim 19 (depends on 11)

The 3D NAND Flash memory device of claim 11, further comprising a group of conductive contact structures vertically extending from the local digit line to the group of the pillar structures, the group of conductive contact structures coupling the local digit line to the group of the pillar structures.

### Claim 20

An electronic system, comprising:
an input device;
an output device;
a processor device operably connected to the input device and the output device; and
a 3D NAND Flash memory device operably connected to the processor device and comprising:
a stack structure comprising tiers each comprising conductive material and insulative material vertically neighboring the conductive material;
strings of memory cells vertically extending through stack structure;
local digit lines vertically overlying the stack structure, each of the local digit lines coupled to a respective group of the strings of memory cells;
source lines vertically overlying the local digit lines;
vertical sense transistors vertically overlying and coupled to the source lines, gate electrodes for the vertical sense transistors coupled to and horizontally extending in parallel with the local digit lines;
vertical read transistors vertically overlying and coupled to the vertical sense transistors, additional gate electrodes for the vertical read transistors horizontally extending orthogonal to the local digit lines;
vertical write transistors at a vertical elevation of the vertical read transistors and coupled to the local digit lines, further gate electrodes for the vertical write transistors horizontally extending orthogonal to the local digit lines; and
global digit lines overlying and coupled to the vertical read transistors and the vertical write transistors, the global digit lines horizontally extending in parallel with the local digit lines.