# US 11,908,511 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,511 B2 - Document ID: US11908511B2 - Status: Granted - Kind: B2 - Application number: 17/645,814 - Filed: 2021-12-23 - Published: 2022-11-17 - Granted: 2024-02-20 - Earliest claimed: 2021-05-12 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Koji Kato - Web page: https://patentgrep.com/patent/US11908511B2 ## CPC - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/408: Address circuits - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/40: characterised by the peripheral circuit region - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/40: characterised by the peripheral circuit region - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device includes a memory string, first wirings electrically connected to the memory string, second wirings electrically connected to the first wirings, transistors electrically connected between the first wirings and the second wirings, and a third wiring connected to gate electrodes of the transistors in common. The memory string includes memory transistors connected in series. Gate electrodes of the memory transistors are connected to the first wirings. The semiconductor memory device executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage that turns the transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation. ## Claims ### Claim 1 A semiconductor memory device comprising: a memory string that includes a plurality of memory transistors connected in series; a plurality of first wirings connected to gate electrodes of the plurality of memory transistors; a plurality of second wirings electrically connected to the plurality of first wirings; a plurality of transistors electrically connected between the plurality of first wirings and the plurality of second wirings; and a third wiring connected to gate electrodes of the plurality of transistors in common, wherein a first read operation is executed in response to an input of a first command set, a second read operation is executed in response to an input of a second command set, a first voltage that turns the plurality of transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation, a third voltage is applied to the plurality of second wirings from the end of the first read operation to the start of the second read operation, a fourth voltage is applied to the plurality of second wirings after the second read operation ends, and the third voltage is larger than the fourth voltage. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein in the first read operation, a plurality of different read voltages are applied to at least one of the plurality of second wirings, and the third voltage is larger than the read voltage largest in the plurality of different read voltages. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein a fifth voltage is applied to at least one of the plurality of second wirings during execution of the first read operation and the second read operation, and the fifth voltage is larger than the third voltage. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein the first command set includes first address data, the second command set includes second address data, a part of the first command set excluding the first address data includes first data, and a part of the second command set excluding the second address data does not include the first data. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the first command set includes first address data, the second command set includes second address data, and a part of the first command set excluding the first address data matches a part of the second command set excluding the second address data. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a substrate; and a plurality of memory strings, wherein the plurality of memory transistors and the plurality of first wirings are arranged in a first direction intersecting with a surface of the substrate, and the plurality of memory strings are arranged in a second direction intersecting with the first direction. ### Claim 7 A semiconductor memory device comprising: a memory string that includes a plurality of memory transistors connected in series; a plurality of first wirings connected to gate electrodes of the plurality of memory transistors; and a plurality of second wirings electrically connected to the plurality of first wirings, wherein a first read operation is executed in response to an input of a first command set, a second read operation is executed in response to an input of a second command set, a first voltage is applied to the plurality of second wirings at a first timing at which the first read operation ends, a second voltage is applied to the plurality of second wirings at a second timing at which the second read operation ends, and the first voltage is larger than the second voltage. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein in the first read operation, a plurality of different read voltages are applied to at least one of the plurality of second wirings, and the first voltage is larger than the read voltage largest in the plurality of different read voltages. ### Claim 9 (depends on 7) The semiconductor memory device according to claim 7, further comprising: a plurality of transistors electrically connected between the plurality of first wirings and the plurality of second wirings; and a third wiring connected to gate electrodes of the plurality of transistors in common, wherein a voltage applied to the third wiring is switched from a third voltage that turns the plurality of transistors ON to a fourth voltage that turns the plurality of transistors OFF at the second timing. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein a voltage applied to the third wiring is maintained to the third voltage at the first timing. ### Claim 11 (depends on 9) The semiconductor memory device according to claim 9, wherein a voltage applied to the third wiring is switched from the third voltage to the fourth voltage at the first timing. ### Claim 12 (depends on 7) The semiconductor memory device according to claim 7, wherein a fifth voltage is applied to at least one of the plurality of second wirings during execution of the first read operation and the second read operation, and the fifth voltage is larger than the first voltage. ### Claim 13 (depends on 7) The semiconductor memory device according to claim 7, wherein the first command set includes first address data, the second command set includes second address data, a part of the first command set excluding the first address data includes first data, and a part of the second command set excluding the second address data does not include the first data. ### Claim 14 (depends on 7) The semiconductor memory device according to claim 7, wherein the first command set includes first address data, the second command set includes second address data, and a part of the first command set excluding the first address data matches a part of the second command set excluding the second address data. ### Claim 15 (depends on 7) The semiconductor memory device according to claim 7, further comprising: a substrate; and a plurality of memory strings, wherein the plurality of memory transistors and the plurality of first wirings are arranged in a first direction intersecting with a surface of the substrate, and the plurality of memory strings are arranged in a second direction intersecting with the first direction. ### Claim 16 A semiconductor memory device comprising: a memory string that includes a plurality of memory transistors connected in series; a plurality of first wirings connected to gate electrodes of the plurality of memory transistors; a plurality of second wirings electrically connected to the plurality of first wirings; and a first bonding pad electrode to which a first voltage is applied, wherein a first read operation is executed in response to an input of a first command set, a second read operation is executed in response to an input of a second command set, when an execution period of the second read operation in a case where the second read operation is executed after an execution of the first read operation is assumed to be a first period, and an average value of a current flowing to the first bonding pad electrode during the execution of the second read operation is assumed to be a first current, when an execution period of latter one of the second read operation in a case where the second read operation is executed after an execution of the second read operation is assumed to be a second period, and an average value of a current flowing to the first bonding pad electrode during the execution of the latter one of the second read operation is assumed to be a second current, the first period is smaller than the second period, or the first current is smaller than the second current, a second voltage is applied to the plurality of second wirings at a first timing at which the first read operation ends, a third voltage is applied to the plurality of second wirings at a second timing at which the second read operation ends, and the second voltage is larger than the third voltage. ### Claim 17 (depends on 16) The semiconductor memory device according to claim 16, further comprising: a substrate; and a plurality of memory strings, wherein the plurality of memory transistors and the plurality of first wirings are arranged in a first direction intersecting with a surface of the substrate, and the plurality of memory strings are arranged in a second direction intersecting with the first direction. ### Claim 18 (depends on 7) The semiconductor memory device according to claim 7, wherein the first voltage is executed in response to the input of the first command set when a predetermined parameter is in an active state. ### Claim 19 (depends on 7) The semiconductor memory device according to claim 7, wherein voltages of the plurality of second wirings are decreased from the first voltage to the second voltage corresponding to a third command set. ### Claim 20 (depends on 7) The semiconductor memory device according to claim 7, further comprising: a timer, wherein voltages of the plurality of second wirings are decreased from the first voltage to the second voltage corresponding to a detection of a certain time of the timer.