# US 11,908,509 B2 · Apparatus with input signal quality feedback

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- Number: US 11,908,509 B2
- Document ID: US11908509B2
- Status: Granted
- Kind: B2
- Application number: 17/701,950
- Filed: 2022-03-23
- Published: 2023-09-28
- Granted: 2024-02-20
- Earliest claimed: 2022-03-23
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: John E. Riley; Scott E. Smith; Jennifer E. Taylor; Gary L. Howe
- Web page: https://patentgrep.com/patent/US11908509B2

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 29/022: {in I/O circuitry}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.

## Claims

### Claim 1

An apparatus, comprising:
a communication buffer configured to receive a clock signal from an external controller;
a logic circuit coupled to the communication buffer and configured to:
count a first number of input transitions of the clock signal for a set time period;
store in one or more sets of latches a count value of the first number of input transitions;
adjust an input bias level for the communication buffer after counting the first number of input transitions;
count a second number of input transitions of the clock signal for the set time period using the adjusted input bias level;
generate a comparison result based on the second number of input transitions and the first number of input transitions; and
a data communication circuit coupled to the logic circuit and configured to:
send the comparison result to the external controller.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the apparatus is further configured to:
determine that the set time period is complete; and
in response to completing the set time period, store in the one or more sets of latches the count value of the first number of input transitions.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the apparatus is further configured to:
determine adjustments to the input bias level for the communication buffer are at a threshold; and
store in the one or more sets of latches the comparison result based on the second number of input transitions and the first number of input transitions.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the apparatus is further configured to:
determine a strength measurement of the clock signal based on the comparison result of the second number of input transitions and the first number of input transitions.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the apparatus is further configured to:
determine a communication circuit setting in response to the comparison result.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the data communication circuit is a DQ output circuit that is used the send the comparison result to the external controller.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the apparatus is a dynamic random-access memory (DRAM) that is coupled to the external controller that comprises a compute express link (CXL) controller.

### Claim 8

A system, comprising:
a controller coupled to a memory array, the controller configured to:
send a clock signal to the memory array;
the memory array operably coupled to at least one processor and configured to:
count a first number of input transitions of the clock signal for a set time period;
store in one or more sets of latches a count value of the first number of input transitions;
adjust an input bias level for a communication buffer after counting the first number of input transitions;
count a second number of input transitions of the clock signal for the set time period using the adjusted input bias level;
generate a comparison result based on the second number of input transitions and the first number of input transitions; and
send the comparison result to the controller.

### Claim 9 (depends on 8)

The system of claim 8, wherein the memory array is further configured to:
determine that the set time period is complete; and
in response to completing the set time period, store in the one or more sets of latches the count value of the first number of input transitions.

### Claim 10 (depends on 8)

The system of claim 8, wherein the memory array is further configured to:
determine adjustments to the input bias level for the communication buffer are at a threshold; and
store in the one or more sets of latches the comparison result based on the second number of input transitions and the first number of input transitions.

### Claim 11 (depends on 8)

The system of claim 8, wherein the memory array is further configured to:
determine a strength measurement of the clock signal based on the comparison result of the second number of input transitions and the first number of input transitions.

### Claim 12 (depends on 8)

The system of claim 8, wherein the memory array is further configured to:
determine a communication circuit setting in response to the comparison result.

### Claim 13 (depends on 8)

The system of claim 8, wherein the memory array uses a DQ output circuit to send the comparison result to the controller.

### Claim 14 (depends on 8)

The system of claim 8, wherein:
the memory array is a dynamic random-access memory (DRAM); and
the controller is a compute express link (CXL) controller.

### Claim 15

A method of operating an apparatus, the method comprising:
counting a first number of input transitions of a clock signal for a set time period;
storing in one or more sets of latches a count value of the first number of input transitions;
adjusting an input bias level for a communication buffer after counting the first number of input transitions;
counting a second number of input transitions of the clock signal for the set time period using the adjusted input bias level;
generating a comparison result based on the second number of input transitions and the first number of input transitions; and
sending the comparison result to an external controller.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
determining that the set time period is complete; and
in response to completing the set time period, storing in the one or more sets of latches the count value of the first number of input transitions.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
determining adjustments to the input bias level for the communication buffer are at a threshold; and
storing in the one or more sets of latches the comparison result based on the second number of input transitions and the first number of input transitions.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
determining a strength measurement of the clock signal based on the comparison result of the second number of input transitions and the first number of input transitions.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
determining a communication circuit setting in response to the comparison result.

### Claim 20 (depends on 15)

The method of claim 15, wherein a DQ output circuit is used to send the comparison result to the external controller.