# US 11,908,508 B2 · Memory with partial array refresh > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,508 B2 - Document ID: US11908508B2 - Status: Granted - Kind: B2 - Application number: 17/684,235 - Filed: 2022-03-01 - Published: 2022-06-16 - Granted: 2024-02-20 - Earliest claimed: 2018-12-31 - Applicants: Lodestar Licensing Group LLC - Inventors: Dale H. Hiscock; Debra M. Bell; Michael Kaminski; Joshua E. Alzheimer; Anthony D. Veches; James S. Rehmeyer - Web page: https://patentgrep.com/patent/US11908508B2 ## CPC - G11C 11/40622: {Partial refresh of memory arrays} - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 16/10: Programming or data input circuits - G11C 11/1675: {Writing or programming circuits or methods} - G11C 11/2275: {Writing or programming circuits or methods} - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 2211/406: Refreshing of dynamic cells - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region. ## Claims ### Claim 1 A memory device, comprising: a memory array including a first memory region and a second memory region, wherein: the memory device is configured to write first data to the memory array in accordance with a programming sequence by writing the first data to volatile memory cells of the first memory region before volatile memory cells of the second memory region, the programming sequence is defined prior to the memory device writing the first data to the volatile memory cells of the first memory region, the programming sequence defines an order of memory locations in the memory device to which the memory device sequentially writes the first data, the first memory region being positioned ahead of the second memory region in the order of the memory locations; and the memory device is configured to update the programming sequence after writing the first data, such that the memory device is configured to write second data to volatile memory cells of the second memory region before writing the second data to volatile memory cells of the first memory region. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the memory device is further configured, after writing the first data and in response to a determination that the first data is not consolidated, to consolidate the first data by rewriting at least a portion of the first data to the first memory region, the second memory region, or a combination thereof. ### Claim 3 (depends on 2) The memory device of claim 2, wherein, to consolidate the first data, the memory device is configured to rewrite at least the portion of the first data from first volatile memory cells of the first memory region to second volatile memory cells of the first memory region that are physically or logically contiguous to third volatile memory cells of the first memory region storing a second portion of the first data. ### Claim 4 (depends on 2) The memory device of claim 2, wherein, to consolidate the first data, the memory device is configured to rewrite at least the portion of the first data from volatile memory cells of the second memory region to volatile memory cells of the first memory region that are physically or logically contiguous to other volatile memory cells of the first memory region storing a second portion of the first data. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the memory device is further configured to determine that the first data stored to the first and/or second memory regions is not consolidated. ### Claim 6 (depends on 1) The memory device of claim 1, wherein, to determine that the first data stored to the first and/or second memory regions is not consolidated, the memory device is configured to determine memory locations of volatile memory cells of the first memory region and/or of the second memory region storing stale first data. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the memory device is configured to update the programming sequence when the second memory region includes a greater number of utilized volatile memory cells than the first memory region. ### Claim 8 A method, comprising: writing first data to a memory array of a memory device in accordance with a programming sequence, wherein the programming sequence defines an order of memory locations in the memory device to which the first data is to be written, wherein writing the first data includes writing the first data to volatile memory cells of a first memory region of the memory array before volatile memory cells of a second memory region of the memory array, wherein the programming sequence is defined prior to writing the first data to the volatile memory cells of the first memory region, wherein the first memory region is positioned before the second memory region in the order of the memory locations; and updating the programming sequence after writing the first data, such that the memory device is configured to write second data to volatile memory cells of the second memory region before writing the second data to volatile memory cells of the first memory region. ### Claim 9 (depends on 8) The method of claim 8, further comprising, after writing the first data, determining that the first data stored to the first and/or second memory regions is not consolidated. ### Claim 10 (depends on 9) The method of claim 9, wherein determining that the first data stored to the first and/or second memory regions is not consolidated includes determining memory locations of volatile memory cells of the first memory region and/or of the second memory region storing stale first data. ### Claim 11 (depends on 8) The method of claim 8, further comprising, after writing the first data and in response to a determination that the first data is not consolidated, consolidating the first data, wherein consolidating the first data includes rewriting at least a portion of the first data to the first memory region, the second memory region, or a combination thereof. ### Claim 12 (depends on 11) The method of claim 11, wherein rewriting at least the portion of the first data includes rewriting at least the portion of the first data from first volatile memory cells of the first memory region to second volatile memory cells of the first memory region that are physically or logically contiguous to third volatile memory cells of the first memory region storing a second portion of the first data. ### Claim 13 (depends on 11) The method of claim 11, wherein rewriting at least the portion of the first data includes rewriting at least the portion of the first data from volatile memory cells of the second memory region to volatile memory cells of the first memory region that are physically or logically contiguous to other volatile memory cells of the first memory region storing a second portion of the first data. ### Claim 14 (depends on 8) The method of claim 8, wherein updating the programming sequence includes updating the programming sequence when the second memory region includes a greater number of utilized volatile memory cells than the first memory region. ### Claim 15 A memory system, comprising: a memory controller; and a dynamic random access memory (DRAM) device operably connected to the memory controller, wherein the DRAM device includes a memory array including a first memory region and a second memory region, wherein: the memory controller and/or the DRAM device are configured to write first data to the memory array in accordance with a programming sequence by writing first data to memory cells of the first memory region before memory cells of the second memory region, the programming sequence is defined prior to the memory controller and/or the DRAM device writing the first data to the memory cells of the first memory region, the programming sequence defines an order of memory locations in the DRAM device to which the memory controller and/or the DRAM device sequentially writes the first data, the first memory region appearing before the second memory region in the order of the memory locations; and the memory controller and/or the DRAM device are configured to update the programming sequence after writing the first data, such that the memory controller and/or the DRAM device are configured to write second data to memory cells of the second memory region before writing the second data to memory cells of the first memory region. ### Claim 16 (depends on 15) The memory system of claim 15, wherein the memory controller and/or the DRAM device are further configured, after writing the first data, to determine that the first data stored to the first and/or the second memory regions is not consolidated. ### Claim 17 (depends on 15) The memory system of claim 15, wherein: the memory controller and/or the DRAM device are further configured, after writing the first data and in response to a determination that the first data stored to the first and/or the second memory regions is not consolidated, reconsolidate at least a portion of the first data; and to reconsolidate at least the portion of the first data, the memory controller and/or the DRAM device are configured to rewrite at least the portion of the first data to memory cells of the first memory region and/or the second memory region that are physically or logically contiguous to other memory cells of the first memory region and/or the second memory region storing a second portion of the first data.