# US 11,908,419 B2 · Gate driver without using carry signal and display device comprising the same

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- Number: US 11,908,419 B2
- Document ID: US11908419B2
- Status: Granted
- Kind: B2
- Application number: 17/966,489
- Filed: 2022-10-14
- Published: 2023-06-01
- Granted: 2024-02-20
- Earliest claimed: 2021-11-30
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: JunHyeok Yang
- Web page: https://patentgrep.com/patent/US11908419B2

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A gate driver and a display device comprising the same are discussed. The gate driver can comprise a plurality of stages for individually driving a plurality of gate lines by a combination of a plurality of group signals, a plurality of block signals, and a plurality of clock signals. Each of the plurality of stages driven independently can include an output buffer including a pull-up transistor configured to generate and output a gate-on level of a scan signal under the control of a first node, and a pull-down transistor configured to generate and output a gate-off level of the scan signal under the control of a second node. Each stage can further include a first controller configured to control the first node, and a second controller configured to control the second node to be opposite to the operation of the first node.

## Claims

### Claim 1

A gate driver comprising:
a plurality of stages configured to individually drive a plurality of gate lines by a combination of a plurality of group signals, a plurality of block signals, and a plurality of clock signals,
wherein each of the plurality of stages driven independently includes:
an output buffer including a pull-up transistor configured to generate and output a gate-on level of a scan signal under control of a first node, and a pull-down transistor configured to generate and output a gate-off level of the scan signal under control of a second node;
a first controller configured to control the first node by the combination of the group signal supplied through a group line among the plurality of group signals, the block signal supplied through a block line among the plurality of block signals, and the clock signal supplied through a clock line among the plurality of clock signals; and
a second controller configured to control the second node to be opposite to an operation of the first node by the combination of the group signal, the block signal, and the clock signal,
wherein:
the plurality of stages include ‘n’ stages by including ‘z’ groups to which the ‘z’ group signals are individually supplied, where n=x×y×z, and z is an integer of 2 or more,
each of the ‘z’ groups includes ‘y’ blocks to which the ‘y’ block signals are individually supplied, where y is an integer of 2 or more, and
each of the ‘y’ blocks includes ‘x’ stages to which the ‘x’ clock signals are individually supplied, where x is an integer of 2 or more.

### Claim 2 (depends on 1)

The gate driver according to claim 1, wherein:
the first controller turns-on the pull-up transistor by activating the first node when all the clock signal, the block signal, and the group signal are in the gate-on level, and
the first controller turns-off the pull-up transistor by deactivating the first node when at least any one of the clock signal, the block signal, and the group signal is in the gate-off level.

### Claim 3 (depends on 1)

The gate driver according to claim 1, wherein:
the second controller turns-off the pull-down transistor by deactivating the second node when all the clock signal, the block signal, and the group signal are in the gate-on level, and
the second controller turns-on the pull-down transistor by activating the second node when at least any one of the clock signal, the block signal, and the group signal is in the gate-off level.

### Claim 4 (depends on 1)

The gate driver according to claim 1, wherein:
the pull-up transistor outputs a first gate-on voltage, supplied through a first power line, to the gate-on level of the scan signal when the pull-up transistor is turned-on by the first controller, and
the pull-down transistor outputs a first gate-off voltage, supplied through a fourth power line, to the gate-off level of the scan signal when the pull-down transistor is turned-on by the second controller.

### Claim 5 (depends on 1)

The gate driver according to claim 1, wherein the first controller includes:
a first transistor controlled by the block signal and configured to output the clock signal;
a second transistor controlled by the group signal and configured to connect the first transistor to the first node; and
a third transistor controlled by a third gate-on voltage supplied through a third power line, and configured to connect a fifth power line supplied with a second gate-off voltage to the first node.

### Claim 6 (depends on 5)

The gate driver according to claim 5, wherein:
the first controller outputs the clock signal to the first node through the first and second transistors when the block signal and the group signal are in the gate-on level, and
the first controller outputs the second gate-off voltage to the first node through the third transistor when at least one of the clock signal, the block signal, and the group signal is in the gate-off level.

### Claim 7 (depends on 1)

The gate driver according to claim 1, wherein the second controller includes:
a fourth transistor controlled by a third gate-on voltage supplied through a third power line, and configured to connect a second power line supplied with a second gate-on voltage to the second node; and
fifth, sixth, and seventh transistors connected in series between the second node and a fifth power line supplied with a second gate-off voltage, and controlled by the clock signal, the block signal, and the group signal,
wherein:
the fifth transistor is controlled by the clock signal and configured to connect the second node to the sixth transistor,
the sixth transistor is controlled by the block signal and configured to connect the fifth transistor to the seventh transistor, and
the seventh transistor is controlled by the group signal and configured to connect the sixth transistor to the second gate-off voltage of the fifth power line.

### Claim 8 (depends on 7)

The gate driver according to claim 7, wherein:
the second controller outputs the second gate-off voltage to the second node through the fifth to seventh transistors when the block signal and the group signal are in the gate-on level, and
the second controller outputs the second gate-on voltage to the second node through the fourth transistor when at least one of the clock signal, the block signal, and the group signal is in the gate-off level.

### Claim 9 (depends on 8)

The gate driver according to claim 8, wherein:
the second gate-off voltage is lower than a first gate-off voltage output by the pull-down transistor, and
the second gate-on voltage is higher than the first gate-on voltage, and is lower than the third gate-on voltage.

### Claim 10 (depends on 1)

The gate driver according to claim 1, wherein:
each of the ‘x’ clock signals has a first section including a gate-on level part of a first period and a gate-off level part of a second period, and the gate-on-level part of the first period is phase-delayed and supplied in sequence,
each of the ‘y’ block signals has a second section including a gate-on level part of a third period and a gate-off level part of a fourth period, the gate-on-level part of the third period is phase-delayed and supplied in sequence, and the third period is set to be longer than time overlapping the first periods of the ‘x’ clock signals, and
each of the ‘z’ group signals has a third section including a gate-on level part of a fifth period and a gate-off level part of a sixth period, the gate-on level part of the fifth period is phase-delayed and supplied in sequence, and the fifth period is set to be longer than time overlapping the third periods of the ‘y’ block signals.

### Claim 11 (depends on 10)

The gate driver according to claim 10, wherein:
the second period is set to be longer than the first period,
the fourth period is set to be longer than the third period, and
the sixth period is set to be longer than the fifth period.

### Claim 12

A display device comprising:
a display panel; and
a gate driver disposed in the display panel,
wherein the gate driver comprises:
a plurality of stages configured to individually drive a plurality of gate lines by a combination of a plurality of group signals, a plurality of block signals, and a plurality of clock signals,
wherein each of the plurality of stages driven independently includes:
an output buffer including a pull-up transistor configured to generate and output a gate-on level of a scan signal under control of a first node, and a pull-down transistor configured to generate and output a gate-off level of the scan signal under control of a second node;
a first controller configured to control the first node by the combination of the group signal supplied through a group line among the plurality of group signals, the block signal supplied through a block line among the plurality of block signals, and the clock signal supplied through a clock line among the plurality of clock signals; and
a second controller configured to control the second node to be opposite to an operation of the first node by the combination of the group signal, the block signal, and the clock signal,
wherein:
the plurality of stages include ‘n’ stages by including ‘z’ groups to which the ‘z’ group signals are individually supplied, where n=x×y×z, and z is an integer of 2 or more,
each of the ‘z’ groups includes ‘y’ blocks to which the ‘y’ block signals are individually supplied, where y is an integer of 2 or more, and
each of the ‘y’ blocks includes ‘x’ stages to which ‘x’ clock signals are individually supplied, where x is an integer of 2 or more.

### Claim 13 (depends on 12)

The display device according to claim 12, wherein:
the first controller turns-on the pull-up transistor by activating the first node when all the clock signal, the block signal, and the group signal are in the gate-on level,
the first controller turns-off the pull-up transistor by deactivating the first node when at least any one of the clock signal, the block signal, and the group signal is in the gate-off level,
the second controller turns-off the pull-down transistor by deactivating the second node when all the clock signal, the block signal, and the group signal are in the gate-on level, and
the second controller turns-on the pull-down transistor by activating the second node when at least any one of the clock signal, the block signal, and the group signal is in the gate-off level.

### Claim 14 (depends on 12)

The display device according to claim 12, wherein:
the pull-up transistor outputs a first gate-on voltage, supplied through a first power line, to the gate-on level of the scan signal when the pull-up transistor is turned-on by the first controller, and
the pull-down transistor outputs a first gate-off voltage, supplied through a fourth power line, to the gate-off level of the scan signal when the pull-down transistor is turned-on by the second controller.

### Claim 15 (depends on 12)

The display device according to claim 12, wherein the first controller includes:
a first transistor controlled by the block signal and configured to output the clock signal;
a second transistor controlled by the group signal and configured to connect the first transistor to the first node; and
a third transistor controlled by a third gate-on voltage supplied through a third power line, and configured to connect a fifth power line supplied with a second gate-off voltage to the first node,
wherein:
the first controller outputs the clock signal to the first node through the first and second transistors when the block signal and the group signal are in the gate-on level, and
the first controller outputs the second gate-off voltage to the first node through the third transistor when at least one of the clock signal, the block signal, and the group signal is in the gate-off level.

### Claim 16 (depends on 12)

The display device according to claim 12, wherein the second controller includes:
a fourth transistor controlled by a third gate-on voltage supplied through a third power line, and configured to connect a second power line supplied with a second gate-on voltage to the second node; and
fifth, sixth, and seventh transistors connected in series between the second node and a fifth power line supplied with a second gate-off voltage, and controlled by the clock signal, the block signal, and the group signal,
wherein:
the fifth transistor is controlled by the clock signal and configured to connect the second node to the sixth transistor,
the sixth transistor is controlled by the block signal and configured to connect the fifth transistor to the seventh transistor, and
the seventh transistor is controlled by the group signal and configured to connect the sixth transistor to the second gate-off voltage of the fifth power line.

### Claim 17 (depends on 16)

The display device according to claim 16, wherein:
the second controller outputs the second gate-off voltage to the second node through the fifth to seventh transistors when the block signal and the group signal are in the gate-on level,
the second controller outputs the second gate-on voltage to the second node through the fourth transistor when at least one of the clock signal, the block signal, and the group signal is in the gate-off level,
the second gate-off voltage is lower than a first gate-off voltage output by the pull-down transistor, and
the second gate-on voltage is higher than the first gate-on voltage, and is lower than the third gate-on voltage.

### Claim 18 (depends on 12)

The display device according to claim 12, wherein:
each of the ‘x’ clock signals has a first section including a gate-on level part of a first period and a gate-off level part of a second period, and the gate-on-level part of the first period is phase-delayed and supplied in sequence,
each of the ‘y’ block signals has a second section including a gate-on level part of a third period and a gate-off level part of a fourth period, the gate-on-level part of the third period is phase-delayed and supplied in sequence, and the third period is set to be longer than time overlapping the first periods of the ‘x’ clock signals, and
each of the ‘z’ group signals has a third section including a gate-on level part of a fifth period and a gate-off level part of a sixth period, the gate-on level part of the fifth period is phase-delayed and supplied in sequence, and the fifth period is set to be longer than time overlapping the third periods of the ‘y’ block signals.

### Claim 19 (depends on 18)

The display device according to claim 18, wherein:
the second period is set to be longer than the first period,
the fourth period is set to be longer than the third period, and
the sixth period is set to be longer than the fifth period.

### Claim 20

A display device comprising:
a display panel; and
a gate driver embedded in the display panel,
wherein the gate driver comprises:
a plurality of stages configured to individually drive a plurality of gate lines by a combination of a plurality of group signals, a plurality of block signals, and a plurality of clock signals,
wherein each of the plurality of stages driven independently includes:
an output buffer including a pull-up transistor configured to generate and output a gate-on level of a scan signal under control of a first node, and a pull-down transistor configured to generate and output a gate-off level of the scan signal under control of a second node;
a first controller configured to control the first node by the combination of the group signal supplied through a group line among the plurality of group signals, the block signal supplied through a block line among the plurality of block signals, and the clock signal supplied through a clock line among the plurality of clock signals; and
a second controller configured to control the second node to be opposite to an operation of the first node by the combination of the group signal, the block signal, and the clock signal,
wherein the first controller includes:
a first transistor controlled by the block signal and configured to output the clock signal;
a second transistor controlled by the group signal and configured to connect the first transistor to the first node; and
a third transistor controlled by a third gate-on voltage supplied through a third power line, and configured to connect a fifth power line supplied with a second gate-off voltage to the first node,
wherein:
the first controller outputs the clock signal to the first node through the first and second transistors when the block signal and the group signal are in the gate-on level, and
the first controller outputs the second gate-off voltage to the first node through the third transistor when at least one of the clock signal, the block signal, and the group signal is in the gate-off level.