# US 11,908,412 B1 · Pixel driving circuit and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,412 B1 - Document ID: US11908412B1 - Status: Granted - Kind: B1 - Application number: 18/340,145 - Filed: 2023-06-23 - Granted: 2024-02-20 - Earliest claimed: 2022-10-11 - Assignees: Hkc Corporation Limited - Applicants: Hkc Corporation Limited - Inventors: Tao Fan; Haijiang Yuan - Web page: https://patentgrep.com/patent/US11908412B1 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements - G09G 3/3659: {the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes} - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0202: Addressing of scan or signal lines - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G 2310/0294: Details of sampling or holding circuits arranged for use in a driver for data electrodes - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel driving circuit and a display panel are provided. The pixel driving circuit includes a scan line, a data line, a capacitor, a switch module, and a driving transistor. A scanning voltage is at a first level in a sampling phase and in a light-emitting phase, and at a second level in a data writing phase. A data voltage is at a high level in the sampling phase, and at a low level in the data writing phase and in the light-emitting phase. The capacitor includes a first capacitor-terminal and a second capacitor-terminal. The driving transistor includes a gate terminal electrically connected with the second capacitor-terminal, a source terminal electrically connected with the scan line, and a drain terminal configured to be electrically connected with the gate terminal in the sampling phase and be disconnected from the gate terminal in the data writing phase. ## Claims ### Claim 1 A pixel driving circuit, having an operating phase comprising a sampling phase, a data writing phase, and a light-emitting phase, the pixel driving circuit comprising: a scan line configured to provide a scanning voltage, wherein the scanning voltage is at a first level in the sampling phase and the light-emitting phase, and at a second level in the data writing phase, one of the first level and the second level is a high level, and another of the first level and the second level is a low level; a data line configured to provide a data voltage, wherein the data voltage is at a high level in the sampling phase, and at a low level in the data writing phase and in the light-emitting phase; a capacitor comprising a first capacitor-terminal and a second capacitor-terminal, wherein the first capacitor-terminal is electrically connected with the data line in both the sampling phase and the data writing phase; a switch module, wherein the switch module has one end electrically connected with the data line and another end electrically connected with the first capacitor-terminal, the switch module is configured to be turned on in the sampling phase and the data writing phase, and turned off in the light-emitting phase, and the switch module comprises a first switch, the first switch comprises a first control terminal, a first terminal, and a second terminal, the first terminal is electrically connected with the data line, and the second terminal is electrically connected with the first capacitor-terminal; a driving transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is electrically connected with the scan line, the gate terminal is electrically connected with the second capacitor-terminal, and the drain terminal is configured to be electrically connected with the gate terminal in the sampling phase and be disconnected from the gate terminal in the data writing phase; and a first control signal line electrically connected with the first control terminal, wherein the first control signal line is configured to provide a first control voltage, the first control voltage is at a third level in the sampling phase and the data writing phase, the first control voltage is at a fourth level in the light-emitting phase, one of the third level and the fourth level is a high level, and another of the third level and the fourth level is a low level. ### Claim 2 (depends on 1) The pixel driving circuit of claim 1, further comprising a Light-Emitting Diode (LED), the LED has a positive terminal and a negative terminal, the negative terminal is grounded, and the positive terminal is configured to be disconnected from the drain terminal in both the sampling phase and the data writing phase; and the positive terminal is configured to be electrically connected with the drain terminal in the light-emitting phase. ### Claim 3 (depends on 2) The pixel driving circuit of claim 2, wherein the switch module comprises a second switch and a third switch, the second switch comprises a second control terminal, a third terminal, and a fourth terminal, and the third switch comprises a third control terminal, a fifth terminal, and a sixth terminal; the third terminal and the fifth terminal each are electrically connected with the data line, and the fourth terminal and the sixth terminal each are electrically connected with the first capacitor-terminal; and the second control terminal is electrically connected with the scan line, the pixel driving circuit further comprises a second control signal line electrically connected with the third control terminal, the second control signal line is configured to provide a second control voltage, the second control voltage is at a fifth level in the sampling phase, the second control voltage is at a sixth level in the data writing phase and the light-emitting phase, one of the fifth level and the sixth level is a high level, and another of the fifth level and the sixth level is a low level. ### Claim 4 (depends on 3) The pixel driving circuit of claim 3, further comprising a fourth switch, wherein the fourth switch comprises a fourth control terminal, a seventh terminal, and an eighth terminal, the seventh terminal is electrically connected with the gate terminal, the eighth terminal is electrically connected with the drain terminal, and the fourth control terminal is electrically connected with the second control signal line. ### Claim 5 (depends on 4) The pixel driving circuit of claim 4, further comprising a fifth switch, wherein the fifth switch comprises a fifth control terminal, a ninth terminal, and a tenth terminal, the ninth terminal is electrically connected with the drain terminal, and the tenth terminal is electrically connected with the positive terminal; and the pixel driving circuit further comprises a third control signal line electrically connected with the fifth control terminal, the third control signal line is configured to provide a third control voltage, the third control voltage is at a seventh level in the sampling phase and the data writing phase, the third control voltage is at an eighth level in the light-emitting phase, one of the seventh level and the eighth level is a high level, and another of the seventh level and the eighth level is a low level. ### Claim 6 (depends on 5) The pixel driving circuit of claim 5, wherein the driving transistor and the second switch each are a P-type Thin Film Transistor (TFT), the third switch, the fourth switch, and the fifth switch each are an N-type TFT, the fifth level is the high level, the sixth level is the low level, the seventh level is the low level, and the eighth level is the high level. ### Claim 7 (depends on 5) The pixel driving circuit of claim 5, wherein the driving transistor, the second switch, the third switch, the fourth switch, and the fifth switch each are a P-type TFT, the fifth level is the low level, the sixth level is the high level, the seventh level is the high level, and the eighth level is the low level. ### Claim 8 A display panel comprising a pixel driving circuit, wherein the pixel driving circuit has an operating phase comprising a sampling phase, a data writing phase, and a light-emitting phase, and the pixel driving circuit comprises: a scan line configured to provide a scanning voltage, wherein the scanning voltage is at a first level in the sampling phase and the light-emitting phase, and at a second level in the data writing phase, one of the first level and the second level is a high level, and another of the first level and the second level is a low level; a data line configured to provide a data voltage, wherein the data voltage is at a high level in the sampling phase, and at a low level in the data writing phase and in the light-emitting phase; a capacitor comprising a first capacitor-terminal and a second capacitor-terminal, wherein the first capacitor-terminal is electrically connected with the data line in both the sampling phase and the data writing phase; a switch module, wherein the switch module has one end electrically connected with the data line and another end electrically connected with the first capacitor-terminal, the switch module is configured to be turned on in the sampling phase and the data writing phase, and turned off in the light-emitting phase, and the switch module comprises a first switch, the first switch comprises a first control terminal, a first terminal, and a second terminal, the first terminal is electrically connected with the data line, and the second terminal is electrically connected with the first capacitor-terminal; a driving transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the source terminal is electrically connected with the scan line, the gate terminal is electrically connected with the second capacitor-terminal, and the drain terminal is configured to be electrically connected with the gate terminal in the sampling phase and be disconnected from the gate terminal in the data writing phase; and a first control signal line electrically connected with the first control terminal, wherein the first control signal line is configured to provide a first control voltage, the first control voltage is at a third level in the sampling phase and the data writing phase, the first control voltage is at a fourth level in the light-emitting phase, one of the third level and the fourth level is a high level, and another of the third level and the fourth level is a low level. ### Claim 9 (depends on 8) The display panel of claim 8, wherein the pixel driving circuit further comprises a Light-Emitting Diode (LED), the LED has a positive terminal and a negative terminal, the negative terminal is grounded, and the positive terminal is configured to be disconnected from the drain terminal in both the sampling phase and the data writing phase; and the positive terminal is configured to be electrically connected with the drain terminal in the light-emitting phase. ### Claim 10 (depends on 9) The display panel of claim 9, wherein the switch module comprises a second switch and a third switch, the second switch comprises a second control terminal, a third terminal, and a fourth terminal, and the third switch comprises a third control terminal, a fifth terminal, and a sixth terminal; the third terminal and the fifth terminal each are electrically connected with the data line, and the fourth terminal and the sixth terminal each are electrically connected with the first capacitor-terminal; and the second control terminal is electrically connected with the scan line, the pixel driving circuit further comprises a second control signal line electrically connected with the third control terminal, the second control signal line is configured to provide a second control voltage, the second control voltage is at a fifth level in the sampling phase, the second control voltage is at a sixth level in the data writing phase and the light-emitting phase, one of the fifth level and the sixth level is a high level, and another of the fifth level and the sixth level is a low level. ### Claim 11 (depends on 10) The display panel of claim 10, wherein the pixel driving circuit further comprises a fourth switch, the fourth switch comprises a fourth control terminal, a seventh terminal, and an eighth terminal, the seventh terminal is electrically connected with the gate terminal, the eighth terminal is electrically connected with the drain terminal, and the fourth control terminal is electrically connected with the second control signal line. ### Claim 12 (depends on 11) The display panel of claim 11, wherein the pixel driving circuit further comprises a fifth switch, the fifth switch comprises a fifth control terminal, a ninth terminal, and a tenth terminal, the ninth terminal is electrically connected with the drain terminal, and the tenth terminal is electrically connected with the positive terminal; and the pixel driving circuit further comprises a third control signal line electrically connected with the fifth control terminal, the third control signal line is configured to provide a third control voltage, the third control voltage is at a seventh level in the sampling phase and the data writing phase, the third control voltage is at an eighth level in the light-emitting phase, one of the seventh level and the eighth level is a high level, and another of the seventh level and the eighth level is a low level. ### Claim 13 (depends on 12) The display panel of claim 12, wherein the driving transistor and the second switch each are a P-type Thin Film Transistor (TFT), the third switch, the fourth switch, and the fifth switch each are an N-type TFT, the fifth level is the high level, the sixth level is the low level, the seventh level is the low level, and the eighth level is the high level. ### Claim 14 (depends on 12) The display panel of claim 12, wherein the driving transistor, the second switch, the third switch, the fourth switch, and the fifth switch each are a P-type TFT, the fifth level is the low level, the sixth level is the high level, the seventh level is the high level, and the eighth level is the low level.