# US 11,908,405 B2 · Pixel circuit and display device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,405 B2 - Document ID: US11908405B2 - Status: Granted - Kind: B2 - Application number: 17/840,072 - Filed: 2022-06-14 - Published: 2023-01-12 - Granted: 2024-02-20 - Earliest claimed: 2021-07-08 - Assignees: LG Display Co., Ltd. - Applicants: LG Display Co., Ltd. - Inventors: Yong Won Lee; Hyun Soo Lee - Web page: https://patentgrep.com/patent/US11908405B2 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element - G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements - G09G 2230/00: Details of flat display driving waveforms - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2310/0216: Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2320/0295: by monitoring each display pixel - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel circuit and a display device including the same are disclosed. The pixel circuit of this disclosure includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to supply an electric current to a light emitting element; a first switch element configured to be turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the second node; and a second switch element configured to be turned off according to a gate-off voltage of a light emitting control pulse generated in antiphase of the scan pulse. ## Claims ### Claim 1 A pixel circuit comprising: a driving element including a first electrode connected to a first node to which a first constant voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, the driving element configured to supply an electric current to a light emitting element; a first switch element configured to be turned on according to a gate-on voltage of a first gate pulse to supply a data voltage to the second node; a second switch element configured to be turned off according to a gate-off voltage of a second gate pulse; a third switch element configured to be turned on according to a gate-on voltage of a third gate pulse to supply a second constant voltage to the third node; a fourth switch element configured to be turned on according to a gate-on voltage of a fourth gate pulse to apply a third constant voltage to the second node; and a capacitor configured to be connected between the second node and the third node, wherein the second gate pulse is inverted with respect to the gate-off voltage when the third gate pulse is inverted with respect to the gate-on voltage, and the second gate pulse is inverted with respect to the gate-on voltage when the first gate pulse is inverted with respect to the gate-on voltage. ### Claim 2 (depends on 1) The pixel circuit of claim 1, wherein each of the first to fourth switch elements is turned on in response to a gate-on voltage and is turned off in response to a gate-off voltage. ### Claim 3 (depends on 2) The pixel circuit of claim 2, wherein the second gate pulse is inverted to the gate-off voltage when the third gate pulse is inverted to the gate-on voltage, and the second gate pulse is inverted to the gate-on voltage when the first gate pulse is inverted to the gate-on voltage. ### Claim 4 (depends on 3) The pixel circuit of claim 3, wherein the fourth gate pulse is inverted to the gate-on voltage when the third gate pulse is inverted to the gate-on voltage, and the fourth gate pulse is inverted to the gate-off voltage before the second gate pulse is inverted to the gate-on voltage. ### Claim 5 (depends on 4) The pixel circuit of claim 4, wherein the first gate pulse is inverted to the gate-on voltage at a same time as the second gate pulse is inverted to the gate-on voltage, and the first gate pulse is inverted to the gate-off voltage when a voltage of the second gate pulse is the gate-on voltage. ### Claim 6 (depends on 5) The pixel circuit of claim 5, wherein the third gate pulse is inverted to the gate-on voltage at a same time as the second gate pulse is inverted to the gate-off voltage, and the third gate pulse is inverted to the gate-off voltage before the first and second gate pulses are inverted to the gate-on voltage. ### Claim 7 (depends on 1) The pixel circuit of claim 1, wherein the first switch element is connected between a data line to which the data voltage is applied and the second node, wherein the second switch element is connected between the third node and an anode electrode of the light emitting element; wherein the third switch element is connected between the third node and a reference line to which the second constant voltage is applied, and wherein the fourth switch element is connected between the second node and an initialization line to which the third constant voltage. ### Claim 8 (depends on 1) The pixel circuit of claim 1, wherein the first switch element includes a gate electrode to which the first gate pulse is applied, a first electrode connected to a data line to which the data voltage is applied, and a second electrode connected to the second node, wherein the second switch element includes a gate electrode to which the second gate pulse is applied, a first electrode connected to the third node, and a second electrode connected to an anode electrode of the light emitting element, wherein the third switch element includes a gate electrode to which the third gate pulse is applied, a first electrode connected to the third node, and a second electrode connected to a reference line to which the second constant voltage is applied, and wherein the fourth switch element includes a gate electrode to which the fourth gate pulse is applied, a first electrode connected to an initialization line to which the third constant voltage, and a second electrode connected to the second node.