# US 11,908,390 B2 · Display panel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,390 B2 - Document ID: US11908390B2 - Status: Granted - Kind: B2 - Application number: 17/994,597 - Filed: 2022-11-28 - Published: 2023-03-23 - Granted: 2024-02-20 - Earliest claimed: 2020-10-15 - Assignees: Xiamen Tianma Micro-Electronics Co., Ltd. - Applicants: Xiamen Tianma Micro-Electronics Co., Ltd. - Inventors: Yong Yuan - Web page: https://patentgrep.com/patent/US11908390B2 ## CPC - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/043: Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver - G09G 2300/0814: used for selection purposes, e.g. logical AND for partial update - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module, a compensation module and a reset module. The drive module includes a drive transistor. The data write module is connected between a data signal input terminal and a source of the drive transistor. The compensation module is connected between a gate of the drive transistor and the drain of the drive transistor. The rest module is connected between a reset signal terminal and the drain of the drive transistor. The reset module also serves as a bias module. An operation of the pixel circuit includes a reset stage and a bias stage, during the reset stage, the reset module and the compensation module are on. ## Claims ### Claim 1 A display panel, comprising: a pixel circuit and a light-emitting element, wherein the pixel circuit comprises a data write module, a drive module, a compensation module and a reset module; wherein the drive module comprises a drive transistor; wherein the data write module is connected to the drive transistor; wherein the compensation module is connected to the drive transistor; wherein the rest module is connected between a reset signal terminal and the drain of the drive transistor; wherein the reset module is reused as a bias module; wherein an operation of the pixel circuit comprises a reset stage and a bias stage, during the reset stage, the reset module and the compensation module are on, and the reset signal terminal provides a reset signal for the gate of the drive transistor, during the bias stage, the reset module is on, the compensation module is off, and the reset signal terminal provides a bias signal for the drain of the drive transistor; wherein an operation of the display panel comprises at least two data write frames; wherein in the at least two data write frames, bias stages have different durations; a voltage of the bias signal is higher than a voltage of the reset signal. ### Claim 2 (depends on 1) The display panel of claim 1, wherein the operation of the display panel comprises a first data write frame and a second data write frame, in the first data write frame, the bias stage has a duration of t7, and in the second data write frame, the bias stage has a duration of t8, wherein t7>t8≥0. ### Claim 3 (depends on 2) The display panel of claim 2, wherein n second data write frames are comprised between two adjacent first data write frames, wherein n≥1. ### Claim 4 (depends on 1) The display panel of claim 1, wherein the drive transistor is a P-type transistor or the drive transistor is an N-type transistor. ### Claim 5 (depends on 1) The display panel of claim 1, wherein the bias stage comprises N sub-bias stages in sequence, wherein N≥1; wherein among the N sub-bias stages, an interval between two adjacent sub-bias stages is a third interval stage in which the data write module is off. ### Claim 6 (depends on 5) The display panel of claim 5, wherein the bias stage comprises at least two third interval stages, and the at least two third interval stages have different durations. ### Claim 7 (depends on 1) The display panel of claim 1, wherein within a duration of one frame of the display panel, the operation of the pixel circuit comprises a pre-stage and a light emission stage, and within a duration of at least one frame, the pre-stage of the pixel circuit comprises the bias stage; wherein between an end of the reset stage and a start of the bias stage, the pre-stage further comprises a first interval stage, and within the first interval stage, the gate of the drive transistor is disconnected from the reset signal, and the data write module remains off. ### Claim 8 (depends on 7) The display panel of claim 7, wherein the bias stage has a duration of t1, the reset stage has a duration of t3, and the first interval stage has a duration of t4, wherein t1>t4, or t3>t4. ### Claim 9 (depends on 1) The display panel of claim 1, wherein the operation of the display panel further comprises a retention frame, a duration of the bias stage in at least one retention frame is greater than a duration of the bias stage in at least one data write frame. ### Claim 10 (depends on 1) The display panel of claim 1, wherein the pixel circuit further comprises: a reset module configured to selectively provide a reset signal for a gate of the drive transistor; an initialization module configured to selectively provide an initialization signal for the light-emitting element; and a light emission control module configured to selectively control the light-emitting element to enter a light emission stage; wherein the light emission control module comprises a first light emission control module and a second light emission control module, the first light emission control module is connected between a first power signal terminal and the drive transistor, and the second light emission control module is connected between the drive transistor and the light-emitting element; and wherein during the bias stage, at least the second light emission control module remains off; and/or within at least part of a time period of the bias stage, the initialization module remains on. ### Claim 11 (depends on 1) The display panel of claim 1, wherein an operation of the pixel circuit comprises a pre-stage and a light emission stage; a pre-stage of at least one data write frame comprises at least one bias stage, a duration of the pre-stage is T11, and a sum of durations of bias stages in the pre-stage is T22, wherein T22≤⅔×T11. ### Claim 12 A display device comprising a display panel, wherein the display panel comprises: a pixel circuit and a light-emitting element, wherein the pixel circuit comprises a data write module, a drive module, a compensation module and a reset module; wherein the drive module comprises a drive transistor; wherein the data write module is connected to the drive transistor; wherein the compensation module is connected to the drive transistor; wherein the rest module is connected between a reset signal terminal and the drain of the drive transistor; wherein the reset module is reused as a bias module; wherein an operation of the pixel circuit comprises a reset stage and a bias stage, during the reset stage, the reset module and the compensation module are on, and the reset signal terminal provides a reset signal for the gate of the drive transistor, during the bias stage, the reset module is on, the compensation module is off, and the reset signal terminal provides a bias signal for the drain of the drive transistor; wherein an operation of the display panel comprises at least two data write frames; wherein in the at least two data write frames, bias stages have different durations; a voltage of the bias signal is higher than a voltage of the reset signal. ### Claim 13 A display panel, comprising: a pixel circuit and a light-emitting element, wherein the pixel circuit comprises a data write module, a drive module, a compensation module and a reset module; wherein the drive module comprises a drive transistor; wherein the data write module is connected to the drive transistor; wherein the compensation module is connected to the drive transistor; wherein the rest module is connected between a reset signal terminal and the drain of the drive transistor; wherein the reset module is reused as a bias module; wherein an operation of the pixel circuit comprises a reset stage and a bias stage, during the reset stage, the reset module and the compensation module are on, and the reset signal terminal provides a reset signal for the gate of the drive transistor, during the bias stage, the reset module is on, the compensation module is off, and the reset signal terminal provides a bias signal for the drain of the drive transistor; wherein an operation of the display panel comprises at least two data write frames, wherein in the at least two data write frames, bias stages have different durations; the operation of the display panel comprises a first data write frame and a second data write frame, in the first data write frame, the bias stage has a duration of t7, and in the second data write frame, the bias stage has a duration of t8, wherein t7>t8≥0. ### Claim 14 (depends on 13) The display panel of claim 13, wherein n second data write frames are comprised between two adjacent first data write frames, wherein n≥1. ### Claim 15 (depends on 13) The display panel of claim 13, wherein the drive transistor is a P-type transistor or the drive transistor is an N-type transistor. ### Claim 16 (depends on 13) The display panel of claim 13, wherein the bias stage comprises N sub-bias stages in sequence, wherein N≥1; wherein among the N sub-bias stages, an interval between two adjacent sub-bias stages is a third interval stage in which the data write module is off. ### Claim 17 (depends on 16) The display panel of claim 16, wherein the bias stage comprises at least two third interval stages, and the at least two third interval stages have different durations. ### Claim 18 (depends on 13) The display panel of claim 13, wherein the pixel circuit further comprises: a reset module configured to selectively provide a reset signal for a gate of the drive transistor; an initialization module configured to selectively provide an initialization signal for the light-emitting element; and a light emission control module configured to selectively control the light-emitting element to enter a light emission stage; wherein the light emission control module comprises a first light emission control module and a second light emission control module, the first light emission control module is connected between a first power signal terminal and the drive transistor, and the second light emission control module is connected between the drive transistor and the light-emitting element; and wherein during the bias stage, at least the second light emission control module remains off; and/or within at least part of a time period of the bias stage, the initialization module remains on. ### Claim 19 (depends on 13) The display panel of claim 13, wherein an operation of the pixel circuit comprises a pre-stage and a light emission stage; a pre-stage of at least one data write frame comprises at least one bias stage, a duration of the pre-stage is T11, and a sum of durations of bias stages in the pre-stage is T22, wherein T22≤⅔×T11. ### Claim 20 (depends on 13) A display device comprising the display panel of claim 13.