# US 11,908,384 B2 · Method of generating a PWM signal and circuit for generating a PWM signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,384 B2 - Document ID: US11908384B2 - Status: Granted - Kind: B2 - Application number: 17/609,396 - Filed: 2020-04-27 - Published: 2022-06-16 - Granted: 2024-02-20 - Earliest claimed: 2019-05-07 - Assignees: OSRAM Opto Semiconductors GmbH - Applicants: OSRAM Opto Semiconductors GmbH - Inventors: Christopher Soell; Markus Koesler; Jens Richter - Web page: https://patentgrep.com/patent/US11908384B2 ## CPC - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - H05B 45/325: Pulse-width modulation [PWM] - G09G 2310/0264: Details of driving circuits - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2320/064: by time modulation of the brightness of the illumination source - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL ## Abstract A circuit for generating a PWM signal includes a shift register having a plurality of clock-controlled register units. Each clock-controlled register unit has an input and an output. The circuit also includes a write unit configured to set the outputs of the register units each to a designated logical value. The circuit further includes a clock generator configured to drive the register units with a common clock signal. The register units are connected in series. The shift register is configured to output the PWM signal at an output contact. The PWM signal is a chronological sequence of the logical values set in the register units, the PWM signal assumes each of the logical values with the duration of one clock of the clock signal, the clock signal is cyclic, during one cycle the duration of successive clocks changes, and the clock signal is identical per cycle. ## Claims ### Claim 1 A method for generating a PWM signal by a circuit comprising a shift register comprising a plurality of clock-controlled register units each having an input and an output, a write unit configured to set the outputs of the register units each to a designated logic value, and a clock generator configured to output a clock signal, wherein the register units are connected in series, so that in each case a logic value at the output of one of the register units is present at the input of the respectively following register unit, a) wherein the outputs of the register units are each set to a predetermined logical value by the write unit, and b) the register units are operated together by the clock signal, wherein the register units take over the respective logical value of the input at the output with each clock pulse, wherein the clock signal is cyclic, wherein during a cycle the duration of successive clocks increases, wherein the shift register outputs the PWM signal at an output contact, the PWM signal being a chronological sequence of the logic values set in the register units, and the PWM signal assumes each of the logic values with the duration of one clock of the clock signal, and wherein one or more of: ascending ordinal numbers are assigned to the register units starting from the output contact, the output of the register unit with the lowest ordinal number is coupled to the input of the register unit with the highest ordinal number, and between two executions of the process step a) the process step b) is executed over a duration of several cycles; or a holding unit is coupled between the output contact and the output of a first register unit of the plurality of register units, in a first state, the holding unit sets the output contact to the logic value provided at the output of the first register unit, in a second state, the holding unit sets the logical value of the output contact, the holding unit is in the second state during step a), and the holding unit is in the first state during step b). ### Claim 2 (depends on 1) The method according to claim 1, in which the number of clocks of a cycle corresponds to the number of register units. ### Claim 3 (depends on 1) The method according to claim 1, in which process steps a) and b) are repeated alternately. ### Claim 4 (depends on 1) The method according to claim 1, in which, in method step a), the outputs of the register units are set in parallel to a predetermined logic value by the write unit. ### Claim 5 (depends on 1) The method according to claim 1, in which, in method step a), the outputs of the register units are set serially to a predetermined logic value by the write unit. ### Claim 6 (depends on 1) The method of operating a light emitting arrangement comprising: a circuit which is operated according to claim 1, and a light-emitting component which is driven by the PWM signal at the output contact of the circuit, wherein a duty cycle of the PWM signal is predetermined by the logic values predetermined in method step a), and an intensity of the radiation emitted from the light-emitting component is adjusted by the duty cycle. ### Claim 7 (depends on 6) The method of operating a display arrangement comprising a plurality of light emitting arrangements each operated by a method according to claim 6, wherein the light emitting components are each part of a pixel of the display arrangement, and circuits are operated with a common clock signal. ### Claim 8 A circuit for generating a PWM signal, comprising: a shift register comprising a plurality of clock-controlled register units each having an input and an output, a write unit configured to set the outputs of the register units each to a designated logical value, and a clock generator configured to drive the register units by a common clock signal, wherein the register units are connected in series, so that in each case a logic value at one of the outputs of the register units is applied to the input of the respective subsequent register unit, wherein the register units are each configured to accept at their output, with each clock pulse, a logic value applied at their input, wherein the shift register is configured to output the PWM signal at an output contact, wherein the PWM signal is a chronological sequence of the logical values set in the register units, and the PWM signal assumes each of the logical values with the duration of one clock of the clock signal, wherein the clock signal is cyclic, wherein during a cycle the duration of successive clocks increases, wherein the clock signal per cycle is identical, wherein ascending ordinal numbers are assigned to the register units starting from the output contact, and wherein the output of the register unit with the lowest ordinal number is coupled to the input of the register unit with the highest ordinal number. ### Claim 9 (depends on 8) The circuit according to claim 8, wherein a holding unit is connected between the output contact and the shift register, in a first state, the holding unit sets the output contact to the logical value output from the shift register, and in a second state, the holding unit sets the logical value of the output contact. ### Claim 10 (depends on 8) A light emitting arrangement comprising a circuit according to claim 8 and a light emitting component, wherein the light-emitting component can be driven by the PWM signal of the circuit, a duty cycle of the PWM signal can be preset by the write unit, and an intensity of the radiation emitted by the light-emitting component can be adjusted by the duty cycle. ### Claim 11 (depends on 10) The light emitting arrangement according to claim 10 comprising a plurality of circuits, wherein a light-emitting component is assigned to each of the circuits, and the light-emitting components are arranged at nodes of an imaginary regular grid. ### Claim 12 (depends on 11) A display arrangement comprising a light emitting arrangement according to claim 11, wherein the light emitting components are each part of a pixel of the display arrangement. ### Claim 13 A circuit for generating a PWM signal, comprising: a shift register comprising a plurality of clock-controlled register units each having an input and an output, a write unit configured to set the outputs of the register units each to a designated logical value, and a clock generator configured to drive the register units by a common clock signal, wherein the register units are connected in series, so that in each case a logic value at one of the outputs of the register units is applied to the input of the respective subsequent register unit, wherein the register units are each configured to accept at their output, with each clock pulse, a logic value applied at their input, wherein the shift register is configured to output the PWM signal at an output contact, wherein the PWM signal is a chronological sequence of the logical values set in the register units, and the PWM signal assumes each of the logical values with the duration of one clock of the clock signal, wherein the clock signal is cyclic, wherein during a cycle the duration of successive clocks increases, wherein the clock signal per cycle is identical, wherein a holding unit is connected between the output contact and the shift register, wherein in a first state, the holding unit sets the output contact to the logical value output from the shift register, and wherein in a second state, the holding unit sets the logical value of the output contact.