# US 11,908,383 B2 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,383 B2 - Document ID: US11908383B2 - Status: Granted - Kind: B2 - Application number: 18/083,296 - Filed: 2022-12-16 - Published: 2023-11-16 - Granted: 2024-02-20 - Earliest claimed: 2022-05-13 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Kihyun Pyun; Jang-Mi Lee - Web page: https://patentgrep.com/patent/US11908383B2 ## CPC - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 3/3225: using an active matrix - G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)} - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD - G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof - G09G 2360/12: Frame memory handling - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device is disclosed that includes a display panel, a data driver, a timing controller, a memory device, and a power voltage generator. The display panel includes pixels. The data driver is configured to apply data voltages to the pixels. The timing controller is configured to control the data driver, to generate a test strobe signal by shifting a phase of a strobe signal, to perform a test write operation and a test read operation with the memory device based on the test strobe signal, and to increase a power voltage when an error bit occurs in the test write operation and the test read operation. The memory device is configured to sample memory data received from the timing controller using the strobe signal and to store sampled memory data. The power voltage generator is configured to apply the power voltage to the memory device. ## Claims ### Claim 1 A display device comprising: a display panel including pixels; a data driver configured to apply data voltages to the pixels; a timing controller configured to control the data driver, to generate a test strobe signal by shifting a phase of a strobe signal, to perform a test write operation and a test read operation with a memory device based on the test strobe signal, and to increase a power voltage when an error bit occurs in the test write operation and the test read operation; the memory device configured to sample memory data received from the timing controller using the strobe signal and to store sampled memory data; and a power voltage generator configured to apply the power voltage to the memory device. ### Claim 2 (depends on 1) The display device of claim 1, wherein the timing controller is configured to perform the test write operation and the test read operation again when the error bit occurs in the test write operation and the test read operation. ### Claim 3 (depends on 1) The display device of claim 1, wherein the timing controller is configured to stop the test write operation and the test read operation when the error bit does not occur in the test write operation and the test read operation. ### Claim 4 (depends on 3) The display device of claim 3, wherein the timing controller is configured to perform the test write operation and the test read operation when the display device is powered on. ### Claim 5 (depends on 1) The display device of claim 1, wherein the test strobe signal includes a first positive test strobe signal generated by shifting the phase of the strobe signal by a first positive reference phase and a first negative test strobe signal generated by shifting the phase of the strobe signal by a first negative reference phase, and wherein the timing controller is configured to increase the power voltage when the error bit occurs in the test write operation and the test read operation performed based on the first positive test strobe signal or the first negative test strobe signal. ### Claim 6 (depends on 5) The display device of claim 5, wherein the timing controller is configured to perform the test write operation and the test read operation again when the error bit occurs in the test write operation and the test read operation performed based on the first positive test strobe signal or the first negative test strobe signal. ### Claim 7 (depends on 5) The display device of claim 5, wherein the timing controller is configured to stop the test write operation and the test read operation when the error bit does not occur in the test write operation and the test read operation performed based on the first positive test strobe signal and the first negative test strobe signal. ### Claim 8 (depends on 5) The display device of claim 5, wherein the test strobe signal includes a second positive test strobe signal generated by shifting the phase of the strobe signal by a second positive reference phase and a second negative test strobe signal generated by shifting the phase of the strobe signal by a second negative reference phase, wherein the timing controller is configured to increase the power voltage by a first rising value when the error bit occurs in the test write operation and the test read operation performed based on the first positive test strobe signal or the first negative test strobe signal and the error bit does not occur in the test write operation and the test read operation performed based on the second positive test strobe signal and the second negative test strobe signal, and wherein the timing controller is configured to increase the power voltage by a second rising value greater than the first rising value when the error bit occurs in the test write operation and the test read operation performed based on the first positive test strobe signal or the first negative test strobe signal and the error bit occurs in the test write operation and the test read operation performed based on the second positive test strobe signal or the second negative test strobe signal. ### Claim 9 (depends on 8) The display device of claim 8, wherein an absolute value of the second positive reference phase is smaller than an absolute of the first positive reference phase, and wherein an absolute value of the second negative reference phase is smaller than an absolute of the first negative reference phase. ### Claim 10 (depends on 5) The display device of claim 5, wherein the test strobe signal includes a second positive test strobe signal generated by shifting the phase of the strobe signal by a second positive reference phase and a second negative test strobe signal generated by shifting the phase of the strobe signal by a second negative reference phase, wherein the timing controller is configure to maintain the power voltage when the error bit occurs in the test write operation and the test read operation performed based on the first positive test strobe signal or the first negative test strobe signal and the error bit does not occur in the test write operation and the test read operation performed based on the second positive test strobe signal and the second negative test strobe signal, and wherein the timing controller is configured to increase the power voltage when the error bit occurs in the test write operation and the test read operation performed based on the first positive test strobe signal or the first negative test strobe signal and the error bit occurs in the test write operation and the test read operation performed based on the second positive test strobe signal or the second negative test strobe signal. ### Claim 11 (depends on 1) The display device of claim 1, wherein the power voltage is applied to an input/output buffer of the memory device. ### Claim 12 (depends on 11) The display device of claim 11, wherein the power voltage generator is configured to apply the power voltage to the timing controller, and wherein the power voltage is used as a core voltage of the timing controller and a core voltage of the memory device. ### Claim 13 (depends on 1) The display device of claim 1, wherein the power voltage is initialized to an initial voltage when the display device is powered on. ### Claim 14 (depends on 13) The display device of claim 13, wherein the initial voltage is a minimum value of a voltage range of a supply voltage according to an interface standard between the timing controller and the memory device. ### Claim 15 A display device comprising: a display panel including pixels; a data driver configured to apply data voltages to the pixels; a timing controller configured to control the data driver, to generate a test strobe signal by shifting a phase of a strobe signal, to perform a test write operation and a test read operation with a memory device based on the test strobe signal, and to decrease a power voltage when an error bit occurs in the test write operation and the test read operation; the memory device configured to sample memory data received from the timing controller using the strobe signal and to store sampled memory data; and a power voltage generator configured to apply the power voltage to the memory device. ### Claim 16 (depends on 15) The display device of claim 15, wherein the test strobe signal includes a first positive test strobe signal generated by shifting the phase of the strobe signal by a first positive reference phase and a first negative test strobe signal generated by shifting the phase of the strobe signal by a first negative reference phase, and wherein the timing controller is configured to decrease the power voltage when the error bit occurs in the test write operation and the test read operation performed based on the first positive test strobe signal or the first negative test strobe signal. ### Claim 17 (depends on 16) The display device of claim 16, wherein the test strobe signal includes a second positive test strobe signal generated by shifting the phase of the strobe signal by a second positive reference phase and a second negative test strobe signal generated by shifting the phase of the strobe signal by a second negative reference phase, wherein the timing controller is configured to decrease the power voltage by a first falling value when the error bit occurs in the test write operation and the test read operation performed based on the first positive test strobe signal or the first negative test strobe signal and the error bit does not occur in the test write operation and the test read operation performed based on the second positive test strobe signal and the second negative test strobe signal, and wherein the timing controller is configured to decrease the power voltage by a second falling value greater than the first falling value when the error bit occurs in the test write operation and the test read operation performed based on the first positive test strobe signal or the first negative test strobe signal and the error bit occurs in the test write operation and the test read operation performed based on the second positive test strobe signal or the second negative test strobe signal. ### Claim 18 (depends on 17) The display device of claim 17, wherein an absolute value of the second positive reference phase is smaller than an absolute of the first positive reference phase, and wherein an absolute value of the second negative reference phase is smaller than an absolute of the first negative reference phase. ### Claim 19 (depends on 15) The display device of claim 15, wherein the power voltage is initialized to an initial voltage when the display device is powered on. ### Claim 20 (depends on 19) The display device of claim 19, wherein the initial voltage is a maximum value of a voltage range of a supply voltage according to an interface standard between the timing controller and the memory device.