# US 11,908,381 B2 · Systems, methods and devices for providing sequence based display drivers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,381 B2 - Document ID: US11908381B2 - Status: Granted - Kind: B2 - Application number: 17/998,124 - Filed: 2021-05-14 - Published: 2023-06-08 - Granted: 2024-02-20 - Earliest claimed: 2020-05-14 - Assignees: Snap Inc. - Applicants: Snap Inc. - Inventors: Howard V. Goetz; Glen Sands - Web page: https://patentgrep.com/patent/US11908381B2 ## CPC - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)} - G09G 3/2077: {by a combination of two or more gradation control methods} - G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) - G09G 5/363: {Graphics controllers} - G09G 5/399: using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers - G09G 2320/08: Arrangements within a display terminal for setting, manually or automatically, display parameters of the display terminal - G09G 2360/02: Graphics controller able to handle multiple formats, e.g. input or output formats - G09G 2360/12: Frame memory handling - G09G 2360/121: using a cache memory - G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel - G09G 2370/045: using multiple communication channels, e.g. parallel and serial - G09G 2370/10: Use of a protocol of communication by packets in interfaces along the display data pipeline - G09G 2370/12: Use of DVI or HDMI protocol in interfaces along the display data pipeline - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display driver device (210) receives a downloadable “sequence” for dynamically reconfiguring displayed image characteristics in an image system. The display driver device comprises one or more storage devices, for example, memory devices, for storing image data (218) and portions of drive sequences (219) that are downloaded and/or updated in real time depending on various inputs (214). ## Claims ### Claim 1 A display driver, comprising: one or more inputs for receiving image data and drive sequences from one or more external controllers; one or more cache memories for storing the image data; at least two separate sequence memories configured to separately store one or more portions of the drive sequence; a parsing circuit configured to receive the image data and the drive sequences, and to update the one or more cache memories and at least two separate sequence memories in real-time, the separate sequence memories being executed in parallel and asynchronously for different sets of image data; and one or more output circuits for providing the image data configured with the drive sequences to a display device via one or more output interfaces. ### Claim 2 (depends on 1) The display driver of claim 1, wherein at least the one or more inputs, the one or more cache memories, the at least two sequence memories, the parsing circuit, and the one or more output circuits are provided on an integrated circuit. ### Claim 3 (depends on 2) The display driver of claim 2, wherein the integrated circuit comprises an application specific integrated circuit (ASIC). ### Claim 4 (depends on 3) The display driver of claim 3, wherein the ASIC comprises a display driver integrated circuit (DDIC). ### Claim 5 (depends on 1) The display driver of claim 1, wherein the one or more external controllers comprises an image data processing circuit. ### Claim 6 (depends on 5) The display driver of claim 5, wherein the image data processing circuit comprises a graphics processing unit (GPU). ### Claim 7 (depends on 5) The display driver of claim 5, wherein an updated drive sequence is received from the image data processing circuit responsive to changes in the image data. ### Claim 8 (depends on 1) The display driver of claim 1, further comprising a time-base circuit for synchronizing execution of the drive sequences with time events associated with the image data. ### Claim 9 (depends on 8) The display driver of claim 8, wherein the time events comprise video synchronization (VSync) intervals. ### Claim 10 (depends on 9) The display driver of claim 9, wherein the synchronizing comprises executing different combinations of drive sequence instructions at different VSync intervals. ### Claim 11 (depends on 1) The display driver of claim 1, wherein the one or more portions comprise signal modulation characteristics, color durations for pixels, frame-rate, color sub-frame rate, bit-depth, color sequential duty-cycle, color-gamut, gamma, persistence, drive-voltages, illumination timing, illumination intensity, timing of individual bit-planes sent to the display, LookUp Tables (LUTs), and serial port interface (SPI) commands. ### Claim 12 (depends on 11) The display driver of claim 11, wherein the separate sequence memories comprise one or more of a LUT memory, a master sequence memory, or a SPI memory. ### Claim 13 (depends on 1) The display driver of claim 1, wherein the image data is formatted in at least one of a mobile industry processor interface (MIPI) format, a high-definition multimedia interface (HDMI) format, a display port (DP) format, a PCI-express format, a USB format, an Ethernet format, or a Wi-Fi format. ### Claim 14 A method for driving a display, the method comprising: receiving, at a display driver, a first drive sequence from a graphics processing unit (GPU); storing the first drive sequence in a first sequence memory; processing a first one or more image frames received from the GPU using the first drive sequence retrieved from the first sequence memory; responsive to a timer event, receiving a second drive sequence from the GPU; storing the second drive sequence in a second sequence memory; and processing a second one or more image frames received from the GPU using the second drive sequence retrieved from the second sequence memory in parallel with and asynchronously from the retrieval of the first drive sequence from the first sequence memory, wherein the first and second one or more image frames respectively processed by the first and second drive sequences are provided from the display driver to a display device. ### Claim 15 (depends on 14) The method of claim 14, wherein the first sequence memory and second sequence memory comprise one or more memory structures including at least a lookup table (LUT) memory, a master sequence memory, and a serial peripheral interface (SPI) memory. ### Claim 16 (depends on 14) The method of claim 14, wherein the one or more image frames are stored on a memory of the display driver separate from the first sequence memory and second sequence memory. ### Claim 17 (depends on 14) The method of claim 14, wherein a timer increment associated with execution of the first and second drive sequences comprises a video synchronization (VSync) signal. ### Claim 18 (depends on 14) The method of claim 14, wherein a timer increment associated with execution of the first and second drive sequences comprises a time interval that is a function of a portion of a command of one of the first or second drive sequences. ### Claim 19 (depends on 14) The method of claim 14, wherein the one or more image frames comprise video frames. ### Claim 20 A method for driving a display, the method comprising: receiving, at a display driver, a plurality of drive sequences from a graphics processing unit (GPU); storing a first drive sequence of the plurality of drive sequences in a first sequence memory; storing a second drive sequence of the plurality of drive sequences in a second sequence memory; processing a first one or more image frames received from the GPU using the first drive sequence retrieved from the first sequence memory; and processing a second one or more video frames received from the GPU using a second drive sequence retrieved from the second sequence memory in parallel with and asynchronously from the retrieval of the first drive sequence from the first sequence memory, wherein switching from using the first drive sequence to using the second drive sequence is performed responsive to a command from the GPU.