# US 11,908,378 B1 · Gate driving circuit and display panel

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- Number: US 11,908,378 B1
- Document ID: US11908378B1
- Status: Granted
- Kind: B1
- Application number: 18/059,255
- Filed: 2022-11-28
- Granted: 2024-02-20
- Earliest claimed: 2022-11-02
- Assignees: Huizhou China Star Optoelectronics Display Co., Ltd.; Tcl China Star Optoelectronics Technology Co., Ltd.
- Applicants: Huizhou China Star Optoelectronics Display Co., Ltd.; Tcl China Star Optoelectronics Technology Co., Ltd.
- Inventors: Wenbo Shi
- Web page: https://patentgrep.com/patent/US11908378B1

## CPC

- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present application provides a gate driving circuit and a display panel. The gate driving circuit includes a plurality of cascaded gate driving units, where each of the plurality of cascaded gate driving units includes a pull-up control module, an inversion module and a feedback module. The potential of the pull-up node is stepwise increased by the pull-up control module, so that the feedback module can be controlled to be turned off by the inversion module when the potential of the pull-up node is lower, thereby improving a phenomenon of leakage of the pull-up node through the feedback module.

## Claims

### Claim 1

A gate driving circuit, comprising a plurality of cascaded gate driving units, wherein each of the gate driving units comprises:
a pull-up control module, wherein an output terminal of the pull-up control module is connected to a pull-up node, for stepwise increasing a potential of the pull-up node;
an inversion module, wherein an input terminal of the inversion module is connected to the pull-up node, for outputting an anti-leakage control signal in response to an increased potential of the pull-up node; and
a feedback module, wherein a control terminal of the feedback module is connected to an output terminal of the inversion module, one terminal of the feedback module is connected to the pull-up node, and another terminal of the feedback module is connected to a first low potential line, for reducing leakage from the pull-up node to the first low potential line in response to the anti-leakage control signal,
wherein, the pull-up control module includes a pull-up control transistor, wherein one of a source/drain of the pull-up control transistor is connected to a Jth stage scanning line, a gate of the pull-up control transistor is connected to a Jth stage cascade line, and another one of the source/drain of the pull-up control transistor is connected to the pull-up node;
wherein the Jth stage scanning line is configured to transmit a Jth stage scanning signal having a trimmed rising edge, and the Jth stage cascade line is configured to transmit a Jth stage cascade signal having a trimmed rising edge;
wherein each of the gate driving units further includes: a pull-up transistor, wherein one of a source/drain of the pull-up transistor is connected to an Nth stage clock line, a gate of the pull-up transistor is connected to the pull-up node, and another one of the source/drain of the pull-up transistor is connected to an Nth stage scanning line; and a cascade transistor, wherein one of a source/drain of the cascade transistor is connected to the Nth stage clock line, a gate of the cascade transistor is connected to the pull-up node, and another one of the source/drain of the cascade transistor is connected to an Nth stage cascade line;
wherein the Nth stage clock line is configured to transmit an Nth stage clock signal having a trimmed rising edge; the Nth stage scanning line is configured to transmit an Nth stage scanning signal having a trimmed rising edge, a waveform of the Nth stage scanning signal is the same as a waveform of the Jth stage scanning signal and a phase of the Nth stage scanning signal lags behind a phase of the Jth stage scanning signal; a waveform of the Nth stage cascade signal is the same as a waveform of the Jth stage cascade signal, and a phase of the Nth stage cascade signal lags behind a phase of the Jth stage cascade signal; and
wherein, an initial moment of the trimmed rising edge is the same as an initial moment of a rising edge of the Nth stage clock signal in timing, and a ratio of a duration of the trimmed rising edge to a pulse duration of the Nth stage clock signal is greater than or equal to ¼ and less than or equal to ⅓.

### Claim 2 (depends on 1)

The gate driving circuit of claim 1, wherein, the pull-up node is configured to provide a pull-up control signal including at least one step pulse, wherein each step pulse of the at least one step pulse includes a first potential pulse and a second potential pulse in succession, and a potential of the first potential pulse is lower than a potential of the second potential pulse.

### Claim 3 (depends on 2)

The gate driving circuit of claim 2, wherein, each step pulse of the at least one step pulse further includes a third potential pulse following the second potential pulse, the potential of the second potential pulse being lower than a potential of the third potential pulse.

### Claim 4 (depends on 1)

The gate driving circuit of claim 1, wherein, a ratio of a potential of the trimmed rising edge to a pulse amplitude of the Nth stage clock signal is greater than or equal to ⅓ and less than or equal to ⅔.

### Claim 5 (depends on 4)

The gate driving circuit of claim 4, wherein, the ratio of the potential of the trimmed rising edge to the pulse amplitude of the Nth stage clock signal is ½.

### Claim 6 (depends on 1)

The gate driving circuit of claim 1, wherein, the inversion module includes a first inversion sub-module, wherein the first inversion sub-module includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein, one of a source/drain of the first transistor is connected to all of a first low frequency control line, one of a source/drain of the second transistor, and a gate of the first transistor, another one of the source/drain of the first transistor is connected to both a gate of the second transistor and one of a source/drain of the third transistor, another one of the source/drain of the second transistor is connected to one of a source/drain of the fourth transistor, a gate of the third transistor is connected to both the pull-up node and a gate of the fourth transistor, and the first low potential line is connected to both another one of the source/drain of the third transistor and another one of the source/drain of the fourth transistor; and
the feedback module includes a first feedback transistor, wherein one of a source/drain of the first feedback transistor is connected to the pull-up node, a gate of the first feedback transistor is connected to both another one of the source/drain of the second transistor and the one of the source/drain of the fourth transistor, and another one of the source/drain of the first feedback transistor is connected to the first low potential line.

### Claim 7 (depends on 6)

The gate driving circuit of claim 6, wherein, the inversion module further includes a second inversion sub-module, wherein the second inversion sub-module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein, one of a source/drain of the fifth transistor is connected to all of a second low frequency control line, one of a source/drain of the sixth transistor, and a gate of the fifth transistor, another one of the source/drain of the fifth transistor is connected to both a gate of the sixth transistor and one of a source/drain of the seventh transistor, another one of the source/drain of the sixth transistor is connected to one of a source/drain of the eighth transistor, a gate of the seventh transistor is connected to both the pull-up node and a gate of the eighth transistor, and the first low potential line is connected to both another one of the source/drain of the seventh transistor and another one of the source/drain of the eighth transistor; and
the feedback module includes a second feedback transistor, wherein one of a source/drain of the second feedback transistor is connected to the pull-up node, a gate of the second feedback transistor is connected to both another one of the source/drain of the sixth transistor and the one of the source/drain of the eighth transistor, and another one of the source/drain of the second feedback transistor is connected to the first low potential line.

### Claim 8

A gate driving circuit, comprising a plurality of cascaded gate driving units, wherein each of the gate driving units comprises:
a pull-up control transistor, wherein one of a source/drain of the pull-up control transistor is connected to a Jth stage scanning line, a gate of the pull-up control transistor is connected to a Jth stage cascade line, and another one of the source/drain of the pull-up control transistor is connected to the pull-up node;
a first transistor, wherein one of a source/drain of the first transistor is connected to a first low frequency control line and a gate of the first transistor;
a second transistor, wherein one of a source/drain of the second transistor is connected to the one of the source/drain of the first transistor, and a gate of the second transistor is connected to another one of the source/drain of the first transistor;
a third transistor, wherein one of a source/drain of the third transistor is connected to another one of the source/drain of the first transistor, a gate of the third transistor is connected to the pull-up node, and another one of the source/drain of the third transistor is connected to the first low potential line;
a fourth transistor, wherein one of a source/drain of the fourth transistor is connected to another one of the source/drain of the second transistor, a gate of the fourth transistor is connected to the pull-up node, and another one of the source/drain of the fourth transistor is connected to the first low potential line;
a first feedback transistor, wherein one of a source/drain of the first feedback transistor is connected to the pull-up node, a gate of the first feedback transistor is connected to both another one of the source/drain of the second transistor and the one of the source/drain of the fourth transistor, and another one of the source/drain of the first feedback transistor is connected to the first low potential line;
wherein the Jth stage scanning line is configured to transmit a Jth stage scanning signal having a trimmed rising edge, and the Jth stage cascade line is configured to transmit a Jth stage cascade signal having a trimmed rising edge;
wherein each of the gate driving units further includes: a fifth transistor, wherein one of a source/drain of the fifth transistor is connected to both a second low frequency control line and a gate of the fifth transistor; a sixth transistor, wherein, one of a source/drain of the sixth transistor is connected to the one of the source/drain of the fifth transistor, and a gate of the second transistor is connected to another one of the source/drain of the fifth transistor; a seventh transistor, wherein, one of a source/drain of the seventh transistor is connected to another one of the source/drain of the fifth transistor, a gate of the seventh transistor is connected to the pull-up node, and another one of the source/drain of the seventh transistor is connected to the first low potential line; an eighth transistor, wherein, one of a source/drain of the eighth transistor is connected to another one of the source/drain of the sixth transistor, a gate of the eighth transistor is connected to the pull-up node, and another one of the source/drain of the eighth transistor is connected to the first low potential line; and a second feedback transistor, wherein, one of a source/drain of the second feedback transistor is connected to the pull-up node, a gate of the second feedback transistor is connected to both another one of the source/drain of the sixth transistor and the one of the source/drain of the seventh transistor, and another one of the source/drain of the second feedback transistor is connected to the first low potential line;
wherein each of the gate driving units further includes: a pull-up transistor, wherein one of a source/drain of the pull-up transistor is connected to an Nth stage clock line, a gate of the pull-up transistor is connected to the pull-up node, and another one of the source/drain of the pull-up transistor is connected to an Nth stage scanning line; and a cascade transistor, wherein one of a source/drain of the cascade transistor is connected to the Nth stage clock line, a gate of the cascade transistor is connected to the pull-up node, and another one of the source/drain of the cascade transistor is connected to an Nth stage cascade line;
wherein the Nth stage clock line is configured to transmit an Nth stage clock signal having a trimmed rising edge; the Nth stage scanning line is configured to transmit an Nth stage scanning signal having a trimmed rising edge, a waveform of the Nth stage scanning signal is the same as a waveform of the Jth stage scanning signal and a phase of the Nth stage scanning signal lags behind a phase of the Jth stage scanning signal; a waveform of the Nth stage cascade signal is the same as a waveform of the Jth stage cascade signal, and a phase of the Nth stage cascade signal lags behind a phase of the Jth stage cascade signal; and
wherein, an initial moment of the trimmed rising edge is the same as an initial moment of a rising edge of the Nth stage clock signal in timing, and a ratio of a duration of the trimmed rising edge to a pulse duration of the Nth stage clock signal is greater than or equal to ¼ and less than or equal to ⅓.

### Claim 9 (depends on 1)

A display panel, comprising the gate driving circuit according to claim 1.

### Claim 10 (depends on 8)

A display panel, comprising the gate driving circuit according to claim 8.

### Claim 11 (depends on 8)

The gate driving circuit of claim 8, wherein, a ratio of a potential of the trimmed rising edge to a pulse amplitude of the Nth stage clock signal is greater than or equal to ⅓ and less than or equal to ⅔.

### Claim 12 (depends on 11)

The gate driving circuit of claim 11, wherein, the ratio of the potential of the trimmed rising edge to the pulse amplitude of the Nth stage clock signal is ½.

### Claim 13 (depends on 9)

The display panel of claim 9, wherein, a ratio of a potential of the trimmed rising edge to a pulse amplitude of the Nth stage clock signal is greater than or equal to ⅓ and less than or equal to ⅔.

### Claim 14 (depends on 13)

The display panel of claim 13, wherein, the ratio of the potential of the trimmed rising edge to the pulse amplitude of the Nth stage clock signal is ½.

### Claim 15 (depends on 10)

The display panel of claim 10, wherein, a ratio of a potential of the trimmed rising edge to a pulse amplitude of the Nth stage clock signal is greater than or equal to ⅓ and less than or equal to ⅔.

### Claim 16 (depends on 15)

The display panel of claim 15, wherein, the ratio of the potential of the trimmed rising edge to the pulse amplitude of the Nth stage clock signal is ½.