# US 11,908,377 B2 · Repair pixel and display apparatus having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,377 B2 - Document ID: US11908377B2 - Status: Granted - Kind: B2 - Application number: 17/831,442 - Filed: 2022-06-03 - Published: 2023-03-02 - Granted: 2024-02-20 - Earliest claimed: 2021-08-24 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., LTD. - Inventors: Hai-Jung In; Sungmin Son; Jae-Jin Song - Web page: https://patentgrep.com/patent/US11908377B2 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/3208: organic, e.g. using organic light-emitting diodes [OLED] - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current - G09G 2330/08: Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared - G09G 2330/10: Dealing with defective pixels - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A repair pixel and a display apparatus including the repair pixel, the display panel including a repair pixel for a pixel row or a plurality of repair pixels for a pixel row so that repair may be performed using the repair pixel when a bad pixel occurs in the corresponding pixel row. The bad pixel is repaired using the repair pixel so that the yield of the display panel may be enhanced. ## Claims ### Claim 1 A repair pixel comprising: a first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second transistor including a control electrode configured to receive a write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to the first node; a third transistor including a control electrode configured to receive a reference gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the first node; a fourth transistor including a control electrode configured to receive an initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the third node; a fifth transistor including a control electrode configured to receive an emission signal, an input electrode configured to receive a first power voltage, and an output electrode connected to the second node; a sixth transistor including a control electrode configured to receive the emission signal, an input electrode connected to the third node and an output electrode connected to a repair line; and an initialization capacitor including a first electrode connected directly to the third node and a second electrode configured to receive the initialization voltage. ### Claim 2 (depends on 1) The repair pixel of claim 1, further comprising a storage capacitor including a first electrode connected to the first node and a second electrode connected to the third node. ### Claim 3 (depends on 2) The repair pixel of claim 2, further comprising a hold capacitor including a first electrode configured to receive the first power voltage and a second electrode connected to the third node. ### Claim 4 (depends on 3) The repair pixel of claim 3, wherein, in a first duration, the emission signal has an inactive level, the reference gate signal has an active level, the initialization gate signal has the active level, and the write gate signal has the inactive level. ### Claim 5 (depends on 4) The repair pixel of claim 4, wherein, in a second duration subsequent to the first duration, the emission signal has the active level, the reference gate signal has the active level, the initialization gate signal has the inactive level and the write gate signal has the inactive level. ### Claim 6 (depends on 5) The repair pixel of claim 5, wherein, in a third duration subsequent to the second duration, the emission signal has the inactive level, the reference gate signal has the inactive level, the initialization gate signal has the inactive level and the write gate signal has the active level. ### Claim 7 (depends on 6) The repair pixel of claim 6, wherein when the reference voltage is VREF, a threshold voltage of the first transistor is VTH, the data voltage is VDATA, a capacitance of the storage capacitor is CST, a capacitance of the hold capacitor is CHOLD, a capacitance of the initialization capacitor is CI NT, and a voltage of the third node in the third duration is VS, VS = ( VREF - VTH ) + CST CST + CHOLD + CINT ⁢ ( VDATA - VREF ) is satisfied. ### Claim 8 (depends on 6) The repair pixel of claim 6, wherein, in a fourth duration subsequent to the third duration, the emission signal has the inactive level, the reference gate signal has the inactive level, the initialization gate signal has the active level, and the write gate signal has the inactive level. ### Claim 9 (depends on 6) The repair pixel of claim 6, wherein, in a fifth duration subsequent to the third duration, the emission signal has the active level, the reference gate signal has the inactive level, the initialization gate signal has the inactive level, and the write gate signal has the inactive level. ### Claim 10 (depends on 9) The repair pixel of claim 9, wherein, when the reference voltage is VREF, the data voltage is VDATA, a capacitance of the storage capacitor is CST, a capacitance of the hold capacitor is CHOLD, a capacitance of the initialization capacitor is CI NT, a mobility of the first transistor is μ, a capacitance per a unit area of the first transistor is Cox, a width to length ratio of the first transistor is W/L, and a source-drain current of the first transistor in the fifth duration is IDS, IDS = 1 2 ⁢ uCox ⁢ W L ⁢ ( CHOLD + CINT CST + CHOLD + CINT ⁢ ( VDATA - VREF ) ) 2 is satisfied. ### Claim 11 A repair pixel comprising: a first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second transistor including a control electrode configured to receive a write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to the first node; a third transistor including a control electrode configured to receive a reference gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the first node; a fourth transistor including a control electrode configured to receive an initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the third node; a fifth transistor including a control electrode configured to receive an emission signal, an input electrode configured to receive a first power voltage, and an output electrode connected to the second node; a sixth transistor including a control electrode configured to receive the emission signal, an input electrode connected to the third node and an output electrode connected to a repair line; a storage capacitor including a first electrode connected to the first node and a second electrode connected to the third node; and a hold capacitor including a first electrode configured to receive the first power voltage and a second electrode connected to the third node, wherein when the reference voltage is VREF, a threshold voltage of the first transistor is VTH, the data voltage is VDATA, a capacitance of the storage capacitor is CST, a capacitance of the hold capacitor is CHOLD, and a voltage of the third node in the third duration is VS, VS = ( VREF - VTH ) + CST CST + CHOLD ⁢ ( VDATA - VREF ) is satisfied. ### Claim 12 A repair pixel comprising: a first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second transistor including a control electrode configured to receive a write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to the first node; a third transistor including a control electrode configured to receive a reference gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the first node; a fourth transistor including a control electrode configured to receive an initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the third node; a fifth transistor including a control electrode configured to receive an emission signal, an input electrode configured to receive a first power voltage, and an output electrode connected to the second node; a sixth transistor including a control electrode configured to receive the emission signal, an input electrode connected to the third node and an output electrode connected to a repair line; a storage capacitor including a first electrode connected to the first node and a second electrode connected to the third node; and a hold capacitor including a first electrode configured to receive the first power voltage and a second electrode connected to the third node, wherein when the reference voltage is VREF, the data voltage is VDATA, a capacitance of the storage capacitor is CST, a capacitance of the hold capacitor is CHOLD, a mobility of the first transistor is μ, a capacitance per a unit area of the first transistor is Cox, a width to length ratio of the first transistor is W/L, and a source-drain current of the first transistor in the fifth duration is IDS, IDS = 1 2 ⁢ uCox ⁢ W L ⁢ ( CHOLD CST + CHOLD ⁢ ( VDATA - VREF ) ) 2 is satisfied. ### Claim 13 A display apparatus comprising: a display panel including a normal pixel and a repair pixel; a gate driver configured to apply a gate signal to the normal pixel and the repair pixel; a data driver configured to apply a data voltage to the normal pixel and the repair pixel; and an emission driver configured to apply an emission signal to the normal pixel and the repair pixel, wherein the repair pixel comprises: a first transistor including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second transistor including a control electrode configured to receive a write gate signal, an input electrode configured to receive the data voltage, and an output electrode connected to the first node; a third transistor including a control electrode configured to receive a reference gate signal, an input electrode configured to receive a reference voltage, and an output electrode connected to the first node; a fourth transistor including a control electrode configured to receive an initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the third node; a fifth transistor including a control electrode configured to receive the emission signal, an input electrode configured to receive a first power voltage, and an output electrode connected to the second node; a sixth transistor including a control electrode configured to receive the emission signal, an input electrode connected to the third node, and an output electrode connected to a repair line; and an initialization capacitor including a first electrode connected directly to the third node and a second electrode configured to receive the initialization voltage. ### Claim 14 (depends on 13) The display apparatus of claim 13, wherein the repair pixel further comprises a storage capacitor including a first electrode connected to the first node and a second electrode connected to the third node. ### Claim 15 (depends on 14) The display apparatus of claim 14, wherein the repair pixel further comprises a hold capacitor including a first electrode configured to receive the first power voltage and a second electrode connected to the third node. ### Claim 16 (depends on 13) The display apparatus of claim 13, wherein the normal pixel comprises: a first normal transistor including a control electrode connected to a first normal node, an input electrode connected to a second normal node, and an output electrode connected to a third normal node; a second normal transistor including a control electrode configured to receive the write gate signal, an input electrode configured to receive the data voltage, and an output electrode connected to the first normal node; a third normal transistor including a control electrode configured to receive the reference gate signal, an input electrode configured to receive the reference voltage, and an output electrode connected to the first normal node; a fourth normal transistor including a control electrode configured to receive the initialization gate signal, an input electrode configured to receive the initialization voltage, and an output electrode connected to the third normal node; a fifth normal transistor including a control electrode configured to receive the emission signal, an input electrode configured to receive the first power voltage, and an output electrode connected to the second normal node; and a light emitting element including a first electrode connected to the third normal node and a second electrode configured to receive a second power voltage. ### Claim 17 (depends on 16) The display apparatus of claim 16, wherein the normal pixel further comprises: a normal storage capacitor including a first electrode connected to the first normal node and a second electrode connected to the third normal node; and a normal hold capacitor including a first electrode configured to receive the first power voltage and a second electrode connected to the third normal node. ### Claim 18 (depends on 13) The display apparatus of claim 13, wherein the display panel comprises: first normal pixels disposed in a first pixel row; and a first repair pixel disposed in the first pixel row and connected to the first normal pixels to repair a defect of the first normal pixels. ### Claim 19 (depends on 13) The display apparatus of claim 13, wherein the display panel comprises: first left normal pixels disposed in a left portion of a first pixel row; a first repair pixel disposed in the first pixel row and connected to the first left normal pixels to repair a defect of the first left normal pixels; first right normal pixels disposed in a right portion of the first pixel row; and a second repair pixel disposed in the first pixel row and connected to the first right normal pixels to repair a defect of the first right normal pixels.