# US 11,908,374 B2 · Demultiplexer, and display panel and display device having demultiplexer

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- Number: US 11,908,374 B2
- Document ID: US11908374B2
- Status: Granted
- Kind: B2
- Application number: 17/047,530
- Filed: 2020-08-28
- Published: 2023-06-01
- Granted: 2024-02-20
- Earliest claimed: 2020-08-20
- Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Inventors: Wenqiang Yu
- Web page: https://patentgrep.com/patent/US11908374B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A demultiplexer is provided. The demultiplexer includes a plurality of demultiplexer units. Each of the demultiplexer units includes two first type thin film transistors sharing a source electrode, and two second type thin film transistors are disposed between two of the demultiplexer units adjacent to each other. Space utilization of the demultiplexer is improved. A display panel and a display device having the demultiplexer are also provided.

## Claims

### Claim 1

A demultiplexer, comprising a plurality of demultiplexer units, wherein each of the demultiplexer units comprises two first type thin film transistors sharing a source electrode, and two second type thin film transistors are disposed between two of the demultiplexer units adjacent to each other;
wherein the two of the demultiplexer units adjacent to each other are respectively a first demultiplexer unit and a second demultiplexer unit, two first type thin film transistors in the first demultiplexer unit are respectively a first thin film transistor and a second thin film transistor, two first type thin film transistors in the second demultiplexer unit are respectively a third thin film transistor and a fourth thin film transistor, and two second type thin film transistors between the first demultiplexer unit and the second demultiplexer unit are respectively a fifth thin film transistor and a sixth thin film transistor;
the fifth thin film transistor and the second thin film transistor share a drain electrode, and the sixth thin film transistor and the third thin film transistor share another drain electrode;
a gate electrode of the fifth thin film transistor is connected to a gate electrode of the second thin film transistor, and a gate electrode of the sixth thin film transistor is connected to a gate electrode of the third thin film transistor;
the gate electrode of the fifth thin film transistor comprises a first subsection and a second subsection vertically connected to each other, and the first subsection is vertically connected to a middle part of the gate electrode of the second thin film transistor;
the gate electrode of the sixth thin film transistor comprises a third subsection and a fourth subsection vertically connected to each other, and the third subsection is vertically connected to a middle part of the gate electrode of the third thin film transistor;
the gate electrode of the second thin film transistor, the first subsection, and the second subsection are combined to form a first shape, and the first shape is h-shaped; and
the gate electrode of the third thin film transistor, the third subsection, and the fourth subsection are combined to form a second shape, and the second shape is a shape formed by flipping the first shape horizontally and vertically.

### Claim 2 (depends on 1)

The demultiplexer according to claim 1, wherein a source electrode shared by the first thin film transistor and the second thin film transistor is a first source electrode, and another source electrode shared by the third thin film transistor and the fourth thin film transistor is a second source electrode; and
a source electrode of the fifth thin film transistor is connected to the first source electrode, and a source electrode of the sixth thin film transistor is connected to the second source electrode.

### Claim 3 (depends on 2)

The demultiplexer according to claim 2, wherein the source electrode of the fifth thin film transistor comprises a fifth subsection and a sixth subsection vertically connected to each other, and the fifth subsection is vertically connected to a bottom of the first source electrode;
the source electrode of the sixth thin film transistor comprises a seventh subsection and an eighth subsection vertically connected to each other, and the seventh subsection is vertically connected to a top of the second source electrode; and
wherein the seventh subsection is an adapter line.

### Claim 4 (depends on 2)

The demultiplexer according to claim 2, wherein a gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, the gate electrode of the third thin film transistor, a gate electrode of the fourth thin film transistor, the gate electrode of the fifth thin film transistor, and the gate electrode of the sixth thin film transistor are disposed in a first layer;
the first source electrode, the second source electrode, the source electrode of the fifth thin film transistor, and the source electrode of the sixth thin film transistor are disposed in a second layer; and
a drain electrode of the first thin film transistor, the drain electrode of the second thin film transistor, the drain electrode of the third thin film transistor, and a drain electrode of the fourth thin film transistor are disposed in the second layer.

### Claim 5 (depends on 2)

The demultiplexer according to claim 2, wherein a gate electrode of the first thin film transistor and the gate electrode of the third thin film transistor are connected to a first clock signal line, the gate electrode of the second thin film transistor and a gate electrode of the fourth thin film transistor are connected to a second clock signal line, the first source electrode is connected to a first data line, and the second source electrode is connected to a second data line.

### Claim 6

A display panel, comprising a demultiplexer comprising a plurality of demultiplexer units, wherein each of the demultiplexer units comprises two first type thin film transistors sharing a source electrode, and two second type thin film transistors are disposed between two of the demultiplexer units adjacent to each other;
the two of the demultiplexer units adjacent to each other are respectively a first demultiplexer unit and a second demultiplexer unit, two first type thin film transistors in the first demultiplexer unit are respectively a first thin film transistor and a second thin film transistor, two first type thin film transistors in the second demultiplexer unit are respectively a third thin film transistor and a fourth thin film transistor, and two second type thin film transistors between the first demultiplexer unit and the second demultiplexer unit are respectively a fifth thin film transistor and a sixth thin film transistor;
the fifth thin film transistor and the second thin film transistor share a drain electrode, and the sixth thin film transistor and the third thin film transistor share another drain electrode;
a gate electrode of the fifth thin film transistor is connected to a gate electrode of the second thin film transistor, and a gate electrode of the sixth thin film transistor is connected to a gate electrode of the third thin film transistor;
the gate electrode of the fifth thin film transistor comprises a first subsection and a second subsection vertically connected to each other, and the first subsection is vertically connected to a middle part of the gate electrode of the second thin film transistor;
the gate electrode of the sixth thin film transistor comprises a third subsection and a fourth subsection vertically connected to each other, and the third subsection is vertically connected to a middle part of the gate electrode of the third thin film transistor;
the gate electrode of the second thin film transistor, the first subsection, and the second subsection are combined to form a first shape, and the first shape is h-shaped; and
the gate electrode of the third thin film transistor, the third subsection, and the fourth subsection are combined to form a second shape, and the second shape is a shape formed by flipping the first shape horizontally and vertically.

### Claim 7 (depends on 6)

The display panel according to claim 6, wherein a source electrode shared by the first thin film transistor and the second thin film transistor is a first source electrode, and another source electrode shared by the third thin film transistor and the fourth thin film transistor is a second source electrode; and
a source electrode of the fifth thin film transistor is connected to the first source electrode, and a source electrode of the sixth thin film transistor is connected to the second source electrode.

### Claim 8 (depends on 7)

The display panel according to claim 7, wherein the source electrode of the fifth thin film transistor comprises a fifth subsection and a sixth subsection vertically connected to each other, and the fifth subsection is vertically connected to a bottom of the first source electrode;
the source electrode of the sixth thin film transistor comprises a seventh subsection and an eighth subsection vertically connected to each other, and the seventh subsection is vertically connected to a top of the second source electrode; and
wherein the seventh subsection is an adapter line.

### Claim 9 (depends on 7)

The display panel according to claim 7, wherein a gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, the gate electrode of the third thin film transistor, a gate electrode of the fourth thin film transistor, the gate electrode of the fifth thin film transistor, and the gate electrode of the sixth thin film transistor are disposed in a first layer;
the first source electrode, the second source electrode, the source electrode of the fifth thin film transistor, and the source electrode of the sixth thin film transistor are disposed in a second layer; and
a drain electrode of the first thin film transistor, the drain electrode of the second thin film transistor, the drain electrode of the third thin film transistor, and a drain electrode of the fourth thin film transistor are disposed in the second layer.

### Claim 10 (depends on 7)

The display panel according to claim 7, wherein a gate electrode of the first thin film transistor and the gate electrode of the third thin film transistor are connected to a first clock signal line, the gate electrode of the second thin film transistor and a gate electrode of the fourth thin film transistor are connected to a second clock signal line, the first source electrode is connected to a first data line, and the second source electrode is connected to a second data line.

### Claim 11 (depends on 6)

The display panel according to claim 6, being a low temperature polysilicon display panel.

### Claim 12

A display device comprising a display panel, wherein the display panel comprises a demultiplexer comprising a plurality of demultiplexer units, each of the demultiplexer units comprises two first type thin film transistors sharing a source electrode, and two second type thin film transistors are disposed between two of the demultiplexer units adjacent to each other;
the two of the demultiplexer units adjacent to each other are respectively a first demultiplexer unit and a second demultiplexer unit, two first type thin film transistors in the first demultiplexer unit are respectively a first thin film transistor and a second thin film transistor, two first type thin film transistors in the second demultiplexer unit are respectively a third thin film transistor and a fourth thin film transistor, and two second type thin film transistors between the first demultiplexer unit and the second demultiplexer unit are respectively a fifth thin film transistor and a sixth thin film transistor;
the fifth thin film transistor and the second thin film transistor share a drain electrode, and the sixth thin film transistor and the third thin film transistor share another drain electrode;
a gate electrode of the fifth thin film transistor is connected to a gate electrode of the second thin film transistor, and a gate electrode of the sixth thin film transistor is connected to a gate electrode of the third thin film transistor;
the gate electrode of the fifth thin film transistor comprises a first subsection and a second subsection vertically connected to each other, and the first subsection is vertically connected to a middle part of the gate electrode of the second thin film transistor;
the gate electrode of the sixth thin film transistor comprises a third subsection and a fourth subsection vertically connected to each other, and the third subsection is vertically connected to a middle part of the gate electrode of the third thin film transistor;
the gate electrode of the second thin film transistor, the first subsection, and the second subsection are combined to form a first shape, and the first shape is h-shaped; and
the gate electrode of the third thin film transistor, the third subsection, and the fourth subsection are combined to form a second shape, and the second shape is a shape formed by flipping the first shape horizontally and vertically.