# US 11,908,365 B2 · Data driving circuit and a display device including the same

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- Number: US 11,908,365 B2
- Document ID: US11908365B2
- Status: Granted
- Kind: B2
- Application number: 18/075,777
- Filed: 2022-12-06
- Published: 2023-03-30
- Granted: 2024-02-20
- Earliest claimed: 2020-11-10
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Ki Hyun Pyun; Jang Mi Lee; Eun Jin Choi
- Web page: https://patentgrep.com/patent/US11908365B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 3/3275: Details of drivers for data electrodes
- G09G 3/3685: {Details of drivers for data electrodes}
- G09G 3/3688: {suitable for active matrices only}
- G09G 5/008: {Clock recovery}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
- G09G 2310/0281: Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
- G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/02: Improving the quality of display appearance
- G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display device including: a display area including pixels connected to data lines and scan lines, the display area including a plurality of signal output lines connected to each of the scan lines through a contact; a data driver including a first data driving circuit at a side of the display area; a scan driver disposed at the side of the display area; and a timing controller, wherein the first data driving circuit includes: output buffers which respectively output data signals to first to k-th data lines (k is an integer greater than 2) of the data lines; and an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are supplied.

## Claims

### Claim 1

A display device, comprising:
a display area including pixels connected to data lines and scan lines, wherein the display area includes a plurality of signal output lines connected to each of the scan lines through a plurality of contacts;
a data driver including a first data driving circuit disposed at a side of the display area to drive the data lines;
a scan driver disposed at the side of the display area to drive the scan lines; and
a timing controller for controlling the data driver and the scan driver,
wherein the display area includes first to third pixel blocks continuous in a first direction, and
each of the first to third pixel blocks includes first to k-th (where k is an integer greater than 2) data lines included in a driving region,
wherein the first data driving circuit comprises:
output buffers which respectively output data signals to the first to k-tin data lines of the data lines; and
an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are to be supplied and a positional relationship between the contacts and the first to K-th data lines,
wherein the delay times increase in the first direction away from the the driving region or increase in a direction opposite the first direction away from the contacts in the driving region,
wherein times at which the data signals are output from the output buffers to the first to k-th data lines are respectively adjusted based on the delay times,
wherein the plurality of signal output lines comprises:
first output lines connected to each of the scan lines in the first pixel block;
second output lines connected to each of the scan lines in the second pixel block; and
third output lines connected to each of the scan lines in the third pixel block,
wherein the scan lines extend in the first direction, and the first to third output lines extend in a second direction crossing the first direction,
wherein the first output lines connect a first scan line of the scan lines in a first contact among the contacts,
wherein the second output lines connect the first scan line in a second contact among the contacts,
wherein the third output lines connect the first scan line in a third contact among the contacts,
wherein the delay times decrease from the first pixel block to the third pixel block,
wherein a portion of the first scan line between the first contact and the second contact has a largest resistance component, and
wherein a portion of the first scan line on a right side of the third contact has a smallest resistance component.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the output delay controller controls the delay times based on distances between one of the contacts and the first to k-th data lines in the first direction.

### Claim 3 (depends on 1)

The display device of claim 1,
wherein the first output lines connect to a second scan line of the scan lines in a fourth contact among the contacts,
wherein the second output lines connect the second scan line in a fifth contact among the contacts,
wherein the third output lines connect the second scan line in a sixth contact among the contacts, and
wherein the delay times increase from the first pixel block to the third pixel block.

### Claim 4 (depends on 3)

The display device of claim 3,
wherein the second scan line is disposed closer to the scan driver and the data driver than the first scan line.

### Claim 5

A display device, comprising:
a display area including pixels connected to data lines and scan lines, wherein the display area includes a plurality of signal output lines connected to each of the scan lines through a plurality of contacts;
a data driver including a first data driving circuit disposed at a side of the display area to drive the data lines;
a scan driver disposed at the side of the display area to drive the scan lines; and
a timing controller for controlling the data driver and the scan driver,
wherein the display area includes first to third pixel blocks continuous in a first direction, and
each of the first to third pixel blocks includes first to k-th (where k is an integer greater than 2) data lines included in a driving region,
wherein the first data driving circuit comprises;
output buffers which respectively output data signals to the first to k-th data lines of the data lines; and
an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are to be supplied and a positional relationship between the contacts and the first to K-th data lines,
wherein the delay times increase in the first direction away from the contacts in the driving region or increase in a direction opposite the first direction away from the contacts in the driving region,
wherein times at which the data signals are output from the output buffers to the first to k-th data lines are respectively adjusted based on the delay times, and
wherein the output delay controller comprises:
a clock frequency divider which divides a frequency of a data transmission clock supplied from the timing controller to generate a reference clock;
a reference period generator which generates reference periods for delaying an output of the data signals based on a period of the reference clock;
a minimum delay selector which selects one of the reference periods as a minimum delay value based on the position information of the pixel row to which the data signals are to be supplied; and
a delay time determiner which determines the delay times based on the minimum delay value and a delay control signal, and delays and outputs the data signals by the delay times.

### Claim 6

A display device, comprising:
a display area including pixels connected to data lines and scan lines, wherein the display area includes a plurality of signal output lines connected to each of the scan lines through a plurality of contacts;
a data driver including a first data driving circuit disposed in a first driving region to drive a portion of the data lines and a second data driving circuit disposed in a second driving region to drive another portion of the data lines;
a scan driver disposed at the side of the display area to drive the scan lines; and
a timing controller for controlling the data driver and the scan driver,
wherein each of the first data driving circuit and the second data driving circuit comprises:
output buffers which respectively output data signals to the first to k-th data lines of the data lines; and
an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are to be supplied and a positional relationship between the contacts and the first to K-th data lines, and
wherein the data driver independently controls the delay times of the data signals output from the data lines with respect to the first data driving circuit and the second data driving circuit,
wherein the display area includes first to third pixel blocks continuous in a first direction,
wherein each of the first to third pixel blocks includes the first data driving circuit and the second data driving circuit,
wherein the plurality of signal output lines comprises:
first output lines connected to each of the scan lines in the first pixel block;
second output lines connected to each of the scan lines in the second pixel block; and
third output lines connected to each of the scan lines in the third pixel block,
wherein the scan lines extend in the first direction, and the first to third output lines extend in a second direction crossing the first direction,
wherein the first output lines connect a first scan line of the scan lines in a first contact among the contacts,
wherein the second output lines connect the first scan line in a second contact among the contacts,
wherein the third output lines connect the first scan line in a third contact among the contacts,
wherein the delay times decrease from the first pixel block to the third pixel block,
wherein a portion of the first scan line between the first contact and the second contact has a largest resistance component, and
wherein a portion of the first scan line on a right side of the third contact has a smallest resistance component.

### Claim 7 (depends on 6)

The display device of claim 6,
wherein the output delay controller comprises:
a clock frequency divider which divides a frequency of a data transmission clock supplied from the timing controller to generate a reference clock;
a reference period generator which generates reference periods for delaying an output of the data signals based on a period of the reference clock;
a minimum delay selector which selects one of the reference periods as a minimum delay value based on the position information of the pixel row to which the data signals are to be supplied; and
a delay time determiner Which determines the delay times based on the minimum delay value and a delay control signal, and delays and outputs the data signals by the delay times.