# US 11,908,065 B2 · Stack-based ray traversal with dynamic multiple-node iterations

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- Number: US 11,908,065 B2
- Document ID: US11908065B2
- Status: Granted
- Kind: B2
- Application number: 17/844,677
- Filed: 2022-06-20
- Published: 2023-09-21
- Granted: 2024-02-20
- Earliest claimed: 2022-03-21
- Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC
- Applicants: Advanced Micro Devices, Inc.; ATI Technologies ULC
- Inventors: Daniel James Skinner; Michael John Livesley; David William John Pankratz
- Web page: https://patentgrep.com/patent/US11908065B2

## CPC

- G06T 15/06: Ray-tracing
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06T 15/08: Volume rendering
- G06T 17/10: Constructive solid geometry [CSG] using solid primitives, e.g. cylinders, cubes
- G06T 2210/21: Collision detection, intersection
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.

## Claims

### Claim 1

A method for performing ray tracing operations, the method comprising:
detecting that a threshold number of traversal stage work-items of a wavefront have terminated; and
in response to the detecting, increasing intersection test parallelization for non-terminated work-items.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
preserving determinism by enforcing depth first boundary volume hierarchy traversal.

### Claim 3 (depends on 1)

The method of claim 1, wherein increasing the intersection test parallelization includes causing the non-terminated work-items to perform additional ray intersection tests per intersection test iteration.

### Claim 4 (depends on 3)

The method of claim 3, wherein prior to the threshold number of work-items having terminated, work-items are performing one intersection test per intersection test iteration.

### Claim 5 (depends on 4)

The method of claim 4, wherein intersection test iterations comprise iterations of a loop executed by the work-items.

### Claim 6 (depends on 1)

The method of claim 1, wherein work-items terminate upon completing traversal of an acceleration structure for ray tracing.

### Claim 7 (depends on 1)

The method of claim 1, wherein increasing the intersection test parallelization includes requesting an intersection test circuitry to perform multiple intersection tests at least partially concurrently.

### Claim 8 (depends on 7)

The method of claim 7, wherein the intersection test circuitry is configured to execute multiple intersection tests in parallel.

### Claim 9 (depends on 7)

The method of claim 7, wherein the intersection test circuitry is pipelined.

### Claim 10

A system for performing ray tracing operations, the system comprising:
a memory configured to store instructions; and
a processor configured to execute a wavefront, the executing including:
detecting that a threshold number of traversal stage work-items of the wavefront have terminated, and
in response to the detecting, increasing intersection test parallelization for non-terminated work-items.

### Claim 11 (depends on 10)

The system of claim 10, wherein the processor is further configured to:
preserve determinism by enforcing depth first boundary volume hierarchy traversal.

### Claim 12 (depends on 10)

The system of claim 10, wherein increasing the intersection test parallelization includes causing the non-terminated work-items to perform additional ray intersection tests per intersection test iteration.

### Claim 13 (depends on 12)

The system of claim 12, wherein prior to the threshold number of work-items having terminated, work-items are performing one intersection test per intersection test iteration.

### Claim 14 (depends on 13)

The system of claim 13, wherein intersection test iterations comprise iterations of a loop executed by the work-items.

### Claim 15 (depends on 10)

The system of claim 10, wherein work-items terminate upon completing traversal of an acceleration structure for ray tracing.

### Claim 16 (depends on 10)

The system of claim 10, wherein increasing the intersection test parallelization includes requesting an intersection test circuitry to perform multiple intersection tests at least partially concurrently.

### Claim 17 (depends on 16)

The system of claim 16, wherein the intersection test circuitry is configured to execute multiple intersection tests in parallel.

### Claim 18 (depends on 16)

The system of claim 16, wherein the intersection test circuitry is pipelined.

### Claim 19

A non-transitory computer-readable medium storing instructions that when executed by a processor cause the processor to perform operations including:
detecting that a threshold number of traversal stage work-items of a wavefront have terminated; and
in response to the detecting, increasing intersection test parallelization for non-terminated work-items.

### Claim 20 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the instructions further cause the processor to:
preserve determinism by enforcing depth first boundary volume hierarchy traversal.