# US 11,907,754 B2 · System to trigger time-dependent action

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- Number: US 11,907,754 B2
- Document ID: US11907754B2
- Status: Granted
- Kind: B2
- Application number: 17/549,949
- Filed: 2021-12-14
- Published: 2023-06-15
- Granted: 2024-02-20
- Earliest claimed: 2021-12-14
- Assignees: Mellanox Technologies, Ltd.
- Applicants: Mellanox Technologies, Ltd.
- Inventors: Wojciech Wasko; Dotan David Levi; Liron Mula; Natan Manevich
- Web page: https://patentgrep.com/patent/US11907754B2

## CPC

- G06F 9/4825: {Interrupt from clock, e.g. time of day}
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/14: Time supervision arrangements, e.g. real time clock
- G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.

## Claims

### Claim 1

A system comprising:
a memory;
a processing device comprising a device processor; and
a peripheral device, comprising:
an interface to share data with the processing device;
a hardware clock; and
processing circuitry to write respective interrupt signaling messages to the memory without needing corresponding individual respective requests from the device processor for writing each of the respective interrupt signaling messages to the memory, responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.

### Claim 2 (depends on 1)

The system according to claim 1, further comprising at least one other processing device connected to the peripheral device, wherein the at least one other processing device is configured responsively to other interrupt signaling messages being written to the memory, to perform other time-dependent actions.

### Claim 3 (depends on 1)

The system according to claim 1, wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to run a given software program.

### Claim 4 (depends on 1)

The system according to claim 1, wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to pause a given software program.

### Claim 5 (depends on 1)

The system according to claim 1, wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to send a given message.

### Claim 6 (depends on 1)

The system according to claim 1, wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to save a software program context.

### Claim 7 (depends on 1)

The system according to claim 1, wherein the device processor includes at least one of: a central processing unit; a graphics processing unit; a data processing unit; or a network interface controller.

### Claim 8 (depends on 1)

The system according to claim 1, wherein the device processor is configured to request the processing circuitry to commence a process of writing the respective interrupt signaling messages to the memory.

### Claim 9 (depends on 1)

The system according to claim 1, wherein the processing circuitry is configured to discipline the hardware clock from a remote reference clock.

### Claim 10 (depends on 1)

The system according to claim 1, wherein:
the processing device includes a device clock;
the processing circuitry is configured to write the respective interrupt signaling messages to the memory over the interface responsively to respective hardware clock values of the hardware clock and a common schedule known to the processing device and the peripheral device;
the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to:
retrieve respective device clock values from the device clock; and
find the respective hardware clock values at which the respective interrupt signaling messages were written to the memory responsively to the schedule; and
the device processor is configured to:
compute respective time differences between the retrieved respective device clock values and the found respective hardware clock values; and
discipline the device clock responsively to ones of the respective time differences.

### Claim 11 (depends on 1)

The system according to claim 1, wherein the processing circuitry is configured to write the respective interrupt signaling messages in the memory using atomic writes.

### Claim 12 (depends on 10)

The system according to claim 10, wherein the processing device includes an interface controller to:
detect the writing of the respective interrupt signaling messages in the memory;
interrupt processing of the device processor responsively to the detection of each of the respective interrupt signaling messages being written to the memory; and
cause the device processor to:
retrieve the respective device clock values from the device clock;
find the respective hardware clock values at which the respective interrupt signaling messages were written to the memory responsively to the schedule; and
discipline the device clock responsively to the respective ones of the respective time differences.

### Claim 13 (depends on 10)

The system according to claim 10, wherein the device processor is configured to:
compute an average time value responsively to the respective time differences in a time window; and
discipline the device clock responsively to the average time value.

### Claim 14 (depends on 10)

The system according to claim 10, wherein the device processor is configured to:
find a smallest time difference of the respective time differences in a time window; and
discipline the device clock responsively to the smallest time difference.

### Claim 15

A system comprising:
a memory;
a processing device comprising: a device processor; and a device clock; and
a peripheral device, comprising:
an interface to share data with the processing device;
a hardware clock; and
processing circuitry to: discipline the hardware clock from a remote reference clock; retrieve respective hardware clock values from the hardware clock; and write respective clock synchronization messages including the retrieved respective hardware clock values to the memory without needing corresponding individual respective requests from the device processor for writing each of the respective clock synchronization messages to the memory, and wherein the device processor is configured to: retrieve respective device clock values from the device clock responsively to the respective clock synchronization messages being written to the memory; compute respective time differences between the respective hardware clock values included in the respective clock synchronization messages and the respective retrieved device clock values; and discipline the device clock responsively to ones of the respective time differences.

### Claim 16 (depends on 15)

The system according to claim 15, wherein the device processor includes at least one of: a central processing unit; a graphics processing unit; a data processing unit; or a network interface controller.

### Claim 17 (depends on 15)

The system according to claim 15, wherein the device processor is configured to request the processing circuitry of the peripheral device to commence a process of writing the respective clock synchronization messages to the memory.

### Claim 18 (depends on 15)

The system according to claim 15, wherein:
the respective clock synchronization messages are respective interrupt signaling messages; and
the processing device includes an interface controller to detect the writing of the respective clock synchronization messages in the memory and interrupt processing of the device processor responsively to the detection of each of the respective clock synchronization messages being written to the memory, and cause the device processor to: retrieve the respective device clock values from the device clock responsively to the respective clock synchronization messages being written to the memory; compute the respective time differences between the respective hardware clock values included in the respective clock synchronization messages and the respective retrieved device clock values; and discipline the device clock responsively to the ones of the respective time differences.

### Claim 19 (depends on 15)

The system according to claim 15, wherein the device processor is configured to:
monitor the memory for updates;
detect the writing of the respective clock synchronization messages in the memory; and
retrieve the respective device clock values from the device clock responsively to detecting the writing of the respective clock synchronization messages in the memory.

### Claim 20 (depends on 15)

The system according to claim 15, wherein the processing circuitry is configured to write the respective clock synchronization messages in the memory using atomic writes.

### Claim 21

A method comprising:
writing respective interrupt signaling messages to a memory responsively to respective hardware clock values of a hardware clock without needing corresponding individual respective requests for writing each of the respective interrupt signaling messages to the memory; and
performing a time-dependent action responsively to the respective interrupt signaling messages being written to the memory.

### Claim 22 (depends on 21)

The method according to claim 21, further comprising running a given software program responsively to the respective interrupt signaling messages being written to the memory.

### Claim 23 (depends on 21)

The method according to claim 21, further comprising pausing a given software program responsively to the respective interrupt signaling messages being written to the memory.

### Claim 24 (depends on 21)

The method according to claim 21, further comprising sending a given message responsively to the respective interrupt signaling messages being written to the memory.

### Claim 25 (depends on 21)

The method according to claim 21, further comprising saving a software program context responsively to the respective interrupt signaling messages being written to the memory.

### Claim 26 (depends on 21)

The method according to claim 21, further comprising requesting processing circuitry to commence a process of writing the respective interrupt signaling messages to the memory.

### Claim 27 (depends on 21)

The method according to claim 21, wherein the writing includes writing the respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock and a schedule, the method further comprising:
responsively to the respective interrupt signaling messages being written to the memory, retrieving respective device clock values from a device clock and finding the respective hardware clock values at which the respective interrupt signaling messages were written to the memory responsively to the schedule;
computing respective time differences between the retrieved respective device clock values and the found respective hardware clock values; and
disciplining the device clock responsively to ones of the respective time differences.

### Claim 28

A system comprising:
a memory;
a processing device comprising a device processor; and
a peripheral device, comprising:
an interface to share data with the processing device;
a hardware clock; and
processing circuitry to write respective interrupt signaling messages to the memory over the interface, responsively to respective hardware clock values of the hardware clock and a common schedule known to the processing device and the peripheral device, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.