# US 11,907,724 B2 · In-memory trace with overlapping processing and logout > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,724 B2 - Document ID: US11907724B2 - Status: Granted - Kind: B2 - Application number: 17/592,686 - Filed: 2022-02-04 - Published: 2023-08-10 - Granted: 2024-02-20 - Earliest claimed: 2022-02-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Lior Binyamini; Chung-Lung K. Shum; Ludmila Zernakov; Markus Kaltenbach; Jang-Soo Lee - Web page: https://patentgrep.com/patent/US11907724B2 ## CPC - G06F 9/3867: {using instruction pipelines} - G06F 11/3476: {Data logging (G06F11/14, G06F11/2205 take precedence)} - G06F 11/3466: {Performance evaluation by tracing or monitoring} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes. ## Claims ### Claim 1 A computer-implemented method comprising: assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group; assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group; performing a frontend logout to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction after the first group completes processing; performing a backend logout to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction after the second group completes processing; starting a next instruction in the first group of the instruction pipeline before the backend logout completes; and fetching and dispatching a subsequent instruction after the next instruction based on completion of the frontend logout of the next instruction and determining that the one or more trace records from the second group are empty. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, further comprising: blocking the next instruction from starting in the first group of the instruction pipeline until after the frontend logout completes; and blocking the next instruction from starting in the second group of the instruction pipeline until after the backend logout completes for the instruction. ### Claim 3 (depends on 1) The computer-implemented method of claim 1, further comprising: suppressing generation of one or more new trace records by at least one of the one or more units of the instruction pipeline based on the trace controller sending a new trace record inhibit signal to the one or more units. ### Claim 4 (depends on 3) The computer-implemented method of claim 3, wherein the suppressing generation of the one or more new trace records is performed to prevent the next instruction from generating one or more new trace records in the first group until after the backend logout completes for the instruction. ### Claim 5 (depends on 1) The computer-implemented method of claim 1, further comprising: determining an operating mode of the processor based on the instruction being processed; and enabling or disabling overlapped logout processing of the frontend group and the backend group. ### Claim 6 (depends on 1) The computer-implemented method of claim 1, further comprising: skipping the frontend logout based on determining the one or more trace records from the first group contain no new values; and skipping the backend logout based on determining the one or more trace records from the second group contain no new values. ### Claim 7 A system of a processor, the system comprising: an instruction pipeline comprising a plurality of units; and a trace controller comprising circuitry to perform operations comprising: assigning a first group of one or more units of the instruction pipeline of the processor as a frontend group; assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group; performing a frontend logout to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction after the first group completes processing; performing a backend logout to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction after the second group completes processing; starting a next instruction in the first group of the instruction pipeline before the backend logout completes; and suppressing generation of one or more new trace records by at least one of the one or more units of the instruction pipeline based on the trace controller sending a new trace record inhibit signal to the one or more units, wherein the suppressing generation of the one or more new trace records is performed to prevent the next instruction from generating one or more new trace records in the first group until after the backend logout completes for the instruction. ### Claim 8 (depends on 7) The system of claim 7, wherein the trace controller is operable to perform operations comprising: blocking the next instruction from starting in the first group of the instruction pipeline until after the frontend logout completes; and blocking the next instruction from starting in the second group of the instruction pipeline until after the backend logout completes for the instruction. ### Claim 9 (depends on 7) The system of claim 7, wherein the trace controller is operable to perform operations comprising: determining an operating mode of the processor based on the instruction being processed; and enabling or disabling overlapped logout processing of the frontend group and the backend group. ### Claim 10 (depends on 7) The system of claim 7, wherein the trace controller is operable to perform operations comprising: skipping the frontend logout based on determining the one or more trace records from the first group contain no new values; and skipping the backend logout based on determining the one or more trace records from the second group contain no new values. ### Claim 11 (depends on 7) The system of claim 7, wherein the trace controller is operable to perform operations comprising: fetching and dispatching a subsequent instruction after the next instruction based on completion of the frontend logout of the next instruction and determining that the one or more trace records from the second group are empty. ### Claim 12 A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by circuitry of a processor to cause the processor to perform operations comprising: assigning a first group of one or more units of an instruction pipeline of the processor as a frontend group; assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group; performing a frontend logout to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction after the first group completes processing; performing a backend logout to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction after the second group completes processing; starting a next instruction in the first group of the instruction pipeline before the backend logout completes; and fetching and dispatching a subsequent instruction after the next instruction based on completion of the frontend logout of the next instruction and determining that the one or more trace records from the second group are empty. ### Claim 13 (depends on 12) The computer program product of claim 12, wherein the program instructions are executable by the circuitry of the processor to cause the processor to perform operations comprising: blocking the next instruction from starting in the first group of the instruction pipeline until after the frontend logout completes; and blocking the next instruction from starting in the second group of the instruction pipeline until after the backend logout completes for the instruction. ### Claim 14 (depends on 12) The computer program product of claim 12, wherein the program instructions are executable by the circuitry of the processor to cause the processor to perform operations comprising: suppressing generation of one or more new trace records by at least one of the one or more units of the instruction pipeline based on the trace controller sending a new trace record inhibit signal to the one or more units. ### Claim 15 (depends on 12) The computer program product of claim 12, wherein the program instructions are executable by the circuitry of the processor to cause the processor to perform operations comprising: determining an operating mode of the processor based on the instruction being processed; and enabling or disabling overlapped logout processing of the frontend group and the backend group. ### Claim 16 (depends on 12) The computer program product of claim 12, wherein the program instructions are executable by the circuitry of the processor to cause the processor to perform operations comprising: skipping the frontend logout based on determining the one or more trace records from the first group contain no new values; and skipping the backend logout based on determining the one or more trace records from the second group contain no new values. ### Claim 17 (depends on 14) The computer program product of claim 14, wherein the suppressing generation of the one or more new trace records is performed to prevent the next instruction from generating one or more new trace records in the first group until after the backend logout completes for the instruction.