# US 11,907,723 B2 · Operation elimination > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,723 B2 - Document ID: US11907723B2 - Status: Granted - Kind: B2 - Application number: 17/699,326 - Filed: 2022-03-21 - Published: 2023-09-21 - Granted: 2024-02-20 - Earliest claimed: 2022-03-21 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Nicholas Andrew Plante; Joseph Michael Pusdesris; Jungsoo Kim - Web page: https://patentgrep.com/patent/US11907723B2 ## CPC - G06F 9/384: {Register renaming} - G06F 9/30029: {Logical and Boolean instructions, e.g. XOR, NOT} - G06F 9/30079: {Pipeline control instructions, e.g. multicycle NOP} - G06F 9/30112: {comprising data of variable length} - G06F 9/30181: {Instruction operation extension or modification} - G06F 9/3828: {with global bypass, e.g. between pipelines, between clusters} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing apparatus is provided. Rename circuitry performs a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers. Each of the mappings is associated with an elimination field value. Operation elimination circuitry replaces an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set. Operation circuitry responds to a subsequent operation that accesses the destination register when the elimination field value is set; by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result. ## Claims ### Claim 1 A data processing apparatus comprising: rename circuitry configured to perform a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers, wherein each of the mappings is associated with an elimination field value; operation elimination circuitry configured to replace an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set; and operation circuitry configured to respond to a subsequent operation that accesses the destination register while the elimination field value is set, by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result, wherein the elimination field value indicates which of a plurality of actions is to be performed. ### Claim 2 (depends on 1) The data processing apparatus according to claim 1, wherein the operation is replaced by inhibiting insertion of the operation into an instruction queue. ### Claim 3 (depends on 1) The data processing apparatus according to claim 1, wherein the operation circuitry is configured to respond to the subsequent operation that accesses the destination register while the elimination field value is unset, by returning the contents of the source register. ### Claim 4 (depends on 1) The data processing apparatus according to claim 1, wherein the mappings are from logical registers to physical registers; and the new mapping references one of the physical registers corresponding with the source register; and the destination register is one of the logical registers. ### Claim 5 (depends on 1) The data processing apparatus according to claim 1, wherein the operation references zero further source registers. ### Claim 6 (depends on 1) The data processing apparatus according to claim 1, wherein the operation circuitry is configured to perform the action on the contents in one clock cycle. ### Claim 7 (depends on 1) The data processing apparatus according to claim 1, wherein the operation circuitry is configured to perform the action on the contents without using logic gates. ### Claim 8 A data processing apparatus comprising: rename circuitry configured to perform a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers, wherein each of the mappings is associated with an elimination field value; operation elimination circuitry configured to replace an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set; and operation circuitry configured to respond to a subsequent operation that accesses the destination register while the elimination field value is set, by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result, wherein the operation is from the list comprising: bitwise NOT, negate-and-shift, reverse bits, reverse bytes, unsigned extension, and sign extension. ### Claim 9 (depends on 1) The data processing apparatus according to claim 1, wherein the operation is an extension operation. ### Claim 10 (depends on 1) The data processing apparatus according to claim 1, wherein the source register and the destination register have different widths. ### Claim 11 A data processing method comprising: performing a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers, wherein each of the mappings is associated with an elimination field value; replacing an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set; and responding to a subsequent operation that accesses the destination register while the elimination field value is set, by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result, wherein the operation is from the list comprising: bitwise NOT, negate-and-shift, reverse bits, reverse bytes, unsigned extension, and sign extension. ### Claim 12 A non-transitory computer-readable medium to store computer-readable code for fabrication of a data processing apparatus comprising: rename circuitry configured to perform a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers, wherein each of the mappings is associated with an elimination field value; operation elimination circuitry configured to replace an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set; and operation circuitry configured to respond to a subsequent operation that accesses the destination register while the elimination field value is set, by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result, wherein the operation is from the list comprising: bitwise NOT, negate-and-shift, reverse bits, reverse bytes, unsigned extension, and sign extension.