FPGA specialist processing block for machine learning
AssigneeIntel Corporation
InventorsMartin Langhammer, Dongdong Chen, Jason R. Bergendahl
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Abstract
The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
Claims20
A digital signal processing (DSP) block comprising:
- a plurality of columns of weight registers;
- a plurality of inputs configurable to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns of weight registers after being received;
- conversion circuitry configurable to receive a shared exponent for the second plurality of values and convert fixed-point values to floating-point values based on the shared exponent;
- and
- a plurality of multipliers configurable to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
An integrated circuit device, comprising:
- a digital signal processing (DSP) block, comprising:
- a plurality of columns of registers;
- a plurality of inputs configurable to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns of registers after being received;
- conversion circuitry configurable to receive a shared exponent for the second plurality of values and convert fixed-point values to floating-point values based on the shared exponent and
- a plurality of multipliers configurable to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
A system comprising:
- a first digital signal processing (DSP) block;
- and
- a second DSP block communicatively coupled to the first DSP block, wherein the second DSP block comprises:
- a plurality of columns of weight registers;
- a plurality of inputs configurable to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns of weight registers after being received;
- conversion circuitry configurable to receive a shared exponent for the second plurality of values and convert fixed-point values to floating-point values based on the shared exponent and
- a plurality of multipliers configurable to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
Dependencies are inferred from the claim text.