# US 11,907,681 B2 · Semiconductor device and method of controlling the semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,681 B2 - Document ID: US11907681B2 - Status: Granted - Kind: B2 - Application number: 17/569,135 - Filed: 2022-01-05 - Published: 2022-04-28 - Granted: 2024-02-20 - Earliest claimed: 2018-06-15 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Taro Fujii; Takao Toi; Teruhito Tanaka; Katsumi Togawa - Web page: https://patentgrep.com/patent/US11907681B2 ## CPC - G06F 7/544: for evaluating functions by calculation {(G06F7/4824 takes precedence)} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 7/53: in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence) - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor. ## Claims ### Claim 1 A semiconductor system, comprising: a data processor; an accelerator; a first data transfer circuit; a second data transfer circuit; and a central processing unit configured to store descriptors in an external memory, the descriptors instructing operations of the accelerator and the first and second data transfer circuits, wherein the data processor is configured to 1) sequentially receive first input data, 2) perform data processing on the first input data, and 3) sequentially output first output data as a result of the data processing to the first data transfer circuit, wherein the first data transfer circuit is configured to 1) receive the first output data from the data processor and 2) output the first output data to a plurality of arithmetic units grouped as a first arithmetic unit group among a plurality of arithmetic units in a parallel arithmetic part of the accelerator, in accordance with the descriptors from the external memory, wherein the first arithmetic unit group of the parallel arithmetic part of the accelerator is configured to 1) sequentially receive, from the first data transfer circuit, the first output data, 2) perform arithmetic operation in parallel between the first output data and each of a plurality of predetermined data, and 3) output a plurality of arithmetic operation results to the second data transfer circuit, in accordance with the descriptors from the external memory, and wherein the second data transfer circuit is configured to 1) receive the plurality of arithmetic operation results from the accelerator and 2) output, to the data processor, the plurality of arithmetic operation results in order as the first input data, in accordance with the descriptors from the external memory, wherein the data processor is configured to sequentially output second output data in parallel with the first output data, wherein the first data transfer circuit is further configured to selectively output the second output data to a plurality of arithmetic units grouped as a second arithmetic unit group different from the first arithmetic unit group among the plurality of arithmetic units in the parallel arithmetic part of the accelerator, in accordance with the descriptors from the external memory, wherein the second arithmetic unit group is configured to 1) sequentially receive the second output data from the first data transfer circuit and 2) perform arithmetic operation in parallel between the second output data and each of the plurality of predetermined data, in accordance with the descriptors from the external memory, wherein the first data transfer circuit is set to a first mode or a second mode based on processing speed of the accelerator with respect to the processing speed of the data processor, wherein, when the first data transfer circuit is set to the first mode, the first data transfer circuit outputs the first output data and the second output data to the first arithmetic unit group and the second arithmetic unit group, respectively, in accordance with the descriptors from the external memory, and wherein, when the first data transfer circuit is set to the second mode, the first data transfer circuit selects sequentially the first output data and the second output data and outputs selected results to the first arithmetic unit group and the second arithmetic unit group in accordance with the descriptors from the external memory. ### Claim 2 (depends on 1) The semiconductor system according to claim 1, wherein the first output data is inputted in common to each of the plurality of arithmetic units of the first arithmetic unit group, and wherein each of the plurality of arithmetic units of the first arithmetic unit group performs the arithmetic operation between a corresponding one of the plurality of predetermined data and the first output data. ### Claim 3 (depends on 1) The semiconductor system according to claim 1, wherein each of the plurality of arithmetic units of the parallel arithmetic part of the accelerator comprises an adder and a multiplier to perform multiply-and-accumulate operation. ### Claim 4 (depends on 1) The semiconductor system according to claim 1, wherein the second data transfer circuit sequentially outputs a plurality of second arithmetic results by the second arithmetic unit group as second input data to the data processor, and wherein the data processor performs the data processing to the second input data in parallel to the data processing to the first input data. ### Claim 5 (depends on 4) The semiconductor system according to claim 4, wherein the second data transfer circuit outputs the plurality of arithmetic operation results and the plurality of second arithmetic results in order as the first input data. ### Claim 6 (depends on 1) The semiconductor system according to claim 1, wherein the second data transfer circuit is set to a third mode or a fourth mode based on the processing speed of the accelerator with respect to the processing speed of the data processor, wherein, when the second data transfer circuit is set to the third mode, the second data transfer circuit outputs the plurality of arithmetic operation results by the first arithmetic units in order as the first input data, and wherein, when the second data transfer circuit is set to the fourth mode, the second data transfer circuit selects collectively at least two of the plurality of arithmetic operation results to output as the first input data. ### Claim 7 (depends on 1) The semiconductor system according to claim 1, wherein the first data transfer circuit is configured to selectively output the first output data or the second output data to the second arithmetic unit group. ### Claim 8 (depends on 1) The semiconductor system according to claim 1, wherein the first data transfer circuit selects and outputs the first output data and the second output data in order to the first arithmetic unit group and the second arithmetic unit group. ### Claim 9 (depends on 1) The semiconductor system according to claim 1, wherein each of the arithmetic units comprises a plurality of arithmetic circuits and a selector selectively outputting output results of the plurality of arithmetic circuits. ### Claim 10 (depends on 1) The semiconductor system according to claim 1, wherein the data processor sequentially outputs the first output data as a result of the data processing to data read from the external memory, and provides a result of data processing to the first input data sequentially input, to the external memory. ### Claim 11 (depends on 10) The semiconductor system according to claim 10, wherein the data processor comprises a first state transition controller that controls arithmetic operation for generating the first output data, and a second state transition controller that controls arithmetic operation for the first input data, wherein the second state transition controller is different from the first state transition controller. ### Claim 12 (depends on 1) The semiconductor system according to claim 1, wherein the accelerator further comprises a local memory storing the plurality of predetermined data. ### Claim 13 (depends on 12) The semiconductor system according to claim 12, wherein a first set of arithmetic units grouped as the first arithmetic unit group and a second set of arithmetic units grouped as the second arithmetic unit group are supplied with the plurality of predetermined data read out from the local memory in common. ### Claim 14 (depends on 12) The semiconductor system according to claim 12, wherein a first set of arithmetic units in the first arithmetic unit group and a second set of arithmetic units in the second arithmetic unit group are supplied with different predetermined data read out from the local memory, respectively. ### Claim 15 (depends on 1) The semiconductor system according to claim 1, further comprising a Direct Memory Access (DMA) controller configured to read the descriptors from the external memory, and issue operation instructions to the accelerator and the first and second data transfer circuits. ### Claim 16 A semiconductor system, comprising: a data processor configured to perform data processing on first input data sequentially input, and to output first output data as a result of the data processing sequentially; an accelerator having a parallel arithmetic part which receives the first output data sequentially and performs arithmetic operation in parallel between the first output data and each of a plurality of predetermined data; a first data transfer circuit configured to receive a plurality of arithmetic operation results by the accelerator, to output the plurality of arithmetic operation results in order as the first input data; and a central processing unit configured to store descriptors in an external memory, the descriptors instructing operations of the accelerator and the first data transfer circuit, wherein the parallel arithmetic part includes a first arithmetic unit group having a plurality of arithmetic units, wherein the first data transfer circuit outputs a plurality of first arithmetic results by the first arithmetic unit group in order as the first input data, in accordance with the descriptors from the external memory, wherein the first data transfer circuit is set to a first mode or a second mode based on processing speed of the accelerator with respect to the processing speed of the data processor, in accordance with the descriptors from the external memory, wherein, when the first data transfer circuit is set to the first mode, the first data transfer circuit outputs the plurality of first arithmetic results by the first arithmetic units in order as the first input data, in accordance with the descriptors from the external memory, and wherein, when the first data transfer circuit is set to the second mode, the first data transfer unit circuit selects collectively at least two of the plurality of first arithmetic results to output as the first input data in accordance with the descriptors from the external memory. ### Claim 17 (depends on 16) The semiconductor system according to system according to claim 16, further comprising a second data transfer circuit selectively outputting the first output data to the first arithmetic unit group in the parallel arithmetic part. ### Claim 18 (depends on 17) The semiconductor system according to claim 17, wherein the data processor is configured to sequentially output second output data in parallel with the first output data, and wherein the second data transfer circuit is configured to selectively output the second output data to a plurality of arithmetic units grouped as a second arithmetic unit group different from the first arithmetic unit group among the plurality of arithmetic units in the parallel arithmetic part. ### Claim 19 (depends on 18) The semiconductor system according to claim 18, wherein the second data transfer circuit is set to a third mode or a fourth mode based on the processing speed of the accelerator with respect to the processing speed of the data processor, wherein, when the second data transfer circuit is set to the third mode, the second data transfer circuit outputs the first output data and the second output data to the first arithmetic unit group and the second arithmetic unit group, respectively, wherein, when the second data transfer circuit is set to the fourth mode, the second data transfer circuit selects sequentially the first output data and the second output data and outputs selected results to the first arithmetic unit group and the second arithmetic unit group. ### Claim 20 (depends on 17) The semiconductor system according to claim 17, further comprising a Direct Memory Access (DMA) controller configured to read the descriptors from the external memory, and issue operation instructions to the accelerator and the first and second data transfer circuits.