# US 11,907,636 B2 · Integrated circuit layout generation method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,636 B2 - Document ID: US11907636B2 - Status: Granted - Kind: B2 - Application number: 17/860,919 - Filed: 2022-07-08 - Published: 2022-10-27 - Granted: 2024-02-20 - Earliest claimed: 2018-05-02 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Ke-Ying Su; Jon-Hsu Ho; Ke-Wei Su; Liang-Yi Chen; Wen-Hsing Hsieh; Wen-Koi Lai; Keng-Hua Kuo; Kuopei Lu; Lester Chang; Ze-Ming Wu - Web page: https://patentgrep.com/patent/US11907636B2 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes - G03F 1/70: Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging - G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) ## Abstract A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram. ## Claims ### Claim 1 A method of generating an integrated circuit (IC) layout diagram, the method comprising: receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region; determining a second gate resistance value based on the location and the width; using the first and second resistance values by performing an alternating current (AC) simulation based on the IC layout diagram to determine that the IC layout diagram does not comply with a design specification; and based on the non-compliance with the design specification, modifying the IC layout diagram. ### Claim 2 (depends on 1) The method of claim 1, wherein the active region corresponds to a fin field-effect transistor (FinFET), and the determining the second gate resistance value is based on a number of fins of the FinFET. ### Claim 3 (depends on 1) The method of claim 1, wherein the determining that the IC layout diagram does not comply with the design specification comprises the design specification corresponding to a gain, a speed, a noise performance, a transient response time, or a cutoff frequency of an IC device corresponding to the IC layout diagram. ### Claim 4 (depends on 1) The method of claim 1, wherein the modifying the IC layout diagram comprises one or both of changing the location of the gate via along the width or adding a second gate via along the width. ### Claim 5 (depends on 1) The method of claim 1, wherein the determining the second gate resistance value comprises retrieving the second gate resistance value from a file or a database. ### Claim 6 (depends on 1) The method of claim 1, wherein the determining the second gate resistance value comprises generating an index value based on the location and the width. ### Claim 7 (depends on 1) The method of claim 1, wherein the location of the gate via is a first location of a first gate via positioned within the active region and along the width of the gate region, the IC layout diagram comprises a second gate via positioned at a second location within the active region and along the width of the gate region, and the determining the second gate resistance value is further based on the second location. ### Claim 8 (depends on 1) The method of claim 1, wherein the determining the second gate resistance value comprises selecting the gate via from a plurality of gate vias based on the gate via being closer to a predetermined location than another gate via of the plurality of gate vias. ### Claim 9 (depends on 1) The method of claim 1, wherein the using the first and second resistance values comprises using a netlist comprising a first gate terminal node corresponding to the gate region. ### Claim 10 (depends on 9) The method of claim 9, wherein the using the netlist comprises: altering the netlist by adding a second gate terminal node corresponding to the gate region and adding a resistor between the first and second gate terminal nodes, the resistor having a resistance value equal to the first gate resistance value subtracted from the second gate resistance value; and performing the AC simulation by simulating an IC device corresponding to the IC layout diagram in which the AC simulation uses the resistor. ### Claim 11 (depends on 1) The method of claim 1, wherein the modifying the IC layout diagram comprises modifying a netlist corresponding to the IC layout diagram. ### Claim 12 A method of generating an integrated circuit (IC) layout diagram, the method comprising: receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region; determining a second gate resistance value based on the location and the width; altering a netlist by adding a second gate terminal node to a first gate terminal node corresponding to the gate region, and adding a resistor between the first and second gate terminal nodes, the resistor having a resistance value equal to the first gate resistance value subtracted from the second gate resistance value; performing an alternating current (AC) simulation of an IC device corresponding to the IC layout diagram in which the AC simulation uses the resistor; based on the AC simulation, determining that the IC layout diagram does not comply with a design specification; and based on the non-compliance with the design specification, modifying the IC layout diagram. ### Claim 13 (depends on 12) The method of claim 12, wherein the determining that the IC layout diagram does not comply with the design specification comprises determining that the IC layout diagram does not comply with one of a gain, speed, noise performance, transient response time, or cutoff frequency specification. ### Claim 14 (depends on 12) The method of claim 12, wherein the modifying the IC layout diagram comprises: including an additional gate via along the width in the IC layout diagram; and modifying a netlist corresponding to the IC layout diagram. ### Claim 15 (depends on 12) The method of claim 12, further comprising storing the modified IC layout diagram in a storage device. ### Claim 16 A method of generating an integrated circuit (IC) layout diagram, the method comprising: receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region; determining a second gate resistance value based on the location and the width; using the first and second resistance values by performing an alternating current (AC) simulation based on the IC layout diagram to determine that the IC layout diagram does not comply with a design specification; and based on the non-compliance with the design specification, modifying the IC layout diagram, wherein the active region corresponds to a fin field-effect transistor (FinFET), and the determining the second gate resistance value is based on a number of fins of the FinFET. ### Claim 17 (depends on 16) The method of claim 16, wherein the determining the second gate resistance value comprises retrieving the second gate resistance value from a resistance value reference using a first index value based on the number of fins of the FinFET. ### Claim 18 (depends on 17) The method of claim 17, wherein the retrieving the second gate resistance value from the resistance value reference further comprises using a second index value based on the location of the gate via along the width. ### Claim 19 (depends on 16) The method of claim 16, wherein the gate via is one gate via of a plurality of gate vias positioned at a corresponding plurality of locations along the width, and the modifying the IC layout diagram comprises changing one or more locations of the plurality of locations. ### Claim 20 (depends on 16) The method of claim 16, wherein the performing the AC simulation comprises performing the AC simulation corresponding to a gain, a speed, a noise performance, a transient response time, or a cutoff frequency of an IC device corresponding to the IC layout diagram.