# US 11,907,635 B2 · Modeling circuit of field effect transistor for symmetric modeling of electrostatic discharge characteristic, method of designing integrated circuit using the same and method of manufacturing integrated circuit using the same

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- Number: US 11,907,635 B2
- Document ID: US11907635B2
- Status: Granted
- Kind: B2
- Application number: 17/391,458
- Filed: 2021-08-02
- Published: 2022-05-26
- Granted: 2024-02-20
- Earliest claimed: 2020-11-26
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Seongjin Mun; Kiyoung Moon; Hyein Lee
- Web page: https://patentgrep.com/patent/US11907635B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10D 89/813: {specially adapted to provide an electrical current path other than the field-effect induced current path}
- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
- H10D 84/403: {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors}
- H10D 89/811: {using FETs as protective elements}
- H10D 89/815: {involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor}
- G06F 2119/10: Noise analysis or noise optimisation
- H03K 2217/0018: Special modifications or use of the back gate voltage of a FET
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A modeling circuit of a field effect transistor includes a first field effect transistor, a first bipolar transistor, a second bipolar transistor and a substrate resistor. The first bipolar transistor has a collector electrode connected to a first node corresponding to a first electrode of the first field effect transistor, an emitter electrode connected to a second node corresponding to a second electrode of the first field effect transistor, and a base electrode. The second bipolar transistor has a collector electrode connected to the second node, an emitter electrode connected to the first node, and a base electrode connected to the base electrode of the first bipolar transistor. The substrate resistor is connected between the base electrodes of the first and second bipolar transistors and a first surface of a semiconductor substrate on which the first field effect transistor is formed.

## Claims

### Claim 1

A modeling circuit comprising:
a first field effect transistor on a semiconductor substrate, the first field effect transistor including a first electrode and a second electrode;
a first bipolar transistor having a first collector electrode connected to a first node corresponding to the first electrode of the first field effect transistor, a first emitter electrode connected to a second node corresponding to the second electrode of the first field effect transistor, and a first base electrode;
a second bipolar transistor having a second collector electrode connected to the second node, a second emitter electrode connected to the first node, and a second base electrode connected to the first base electrode of the first bipolar transistor; and
a substrate resistor connected between the first and second base electrodes and a first surface of the semiconductor substrate.

### Claim 2 (depends on 1)

The modeling circuit of claim 1, further comprising:
a first resistor connected between the first electrode of the first field effect transistor and the first node;
a second resistor connected between the second electrode of the first field effect transistor and the second node;
a third resistor connected between the first node and a first external connection terminal; and
a fourth resistor connected between the second node and a second external connection terminal.

### Claim 3 (depends on 2)

The modeling circuit of claim 2, wherein:
the first and second resistors correspond to active resistances of the first field effect transistor, and
the third and fourth resistors correspond to parasitic active resistances of the first and second bipolar transistors.

### Claim 4 (depends on 2)

The modeling circuit of claim 2, further comprising:
a first diode and a fifth resistor connected in series between the first node and the first surface of the semiconductor substrate; and
a second diode and a sixth resistor connected in series between the second node and the first surface of the semiconductor substrate.

### Claim 5 (depends on 1)

The modeling circuit of claim 1, wherein the first field effect transistor is configured to be symmetrically modeled based on a forward active characteristic of the first bipolar transistor and a reverse active characteristic of the second bipolar transistor, or
is configured to be symmetrically modeled based on a reverse active characteristic of the first bipolar transistor and a forward active characteristic of the second bipolar transistor.

### Claim 6 (depends on 5)

The modeling circuit of claim 5, wherein each of the first and second bipolar transistors includes a most exquisite transistor model-bipolar junction transistor (MEXTRAM-BJT).

### Claim 7 (depends on 1)

The modeling circuit of claim 1, wherein:
a first terminal corresponds to the first electrode of the first field effect transistor, a second terminal corresponds to the second electrode of the first field effect transistor, a gate terminal corresponds to a gate electrode of the first field effect transistor, and a bulk terminal corresponds to the semiconductor substrate, and
the modeling circuit is configured to have operating characteristics during a first operation mode in which the gate terminal, the second terminal, and the bulk terminal are connected in common be the same as operating characteristics during a second operation mode in which the gate terminal, the first terminal, and the bulk terminal are connected in common.

### Claim 8 (depends on 7)

The modeling circuit of claim 7, wherein a first operating characteristic by a first driving scheme in which a first driving current is applied through the first terminal during the first operation mode is the same as a second operating characteristic by a second driving scheme in which a second driving current is applied through the second terminal during second operation mode.

### Claim 9 (depends on 8)

The modeling circuit of claim 8, wherein the first driving scheme and the second driving scheme correspond to a snapback mode.

### Claim 10 (depends on 8)

The modeling circuit of claim 8, wherein a third operating characteristic by a third driving scheme in which a third driving current is applied through the second terminal during the first operation mode is the same as a fourth operating characteristic by a fourth driving scheme in which a fourth driving current is applied through the first terminal during the second operation mode.

### Claim 11 (depends on 10)

The modeling circuit of claim 10, wherein the third driving scheme and the fourth driving scheme correspond to a diode mode.

### Claim 12 (depends on 7)

The modeling circuit of claim 7, wherein:
in response to the first bipolar transistor being turned on, the second bipolar transistor is turned off, and
in response to the second bipolar transistor being turned on, the first bipolar transistor is turned off.

### Claim 13 (depends on 1)

The modeling circuit of claim 1, wherein:
the first field effect transistor includes an n-type metal oxide semiconductor field effect transistor (NMOSFET), and
each of the first and second bipolar transistors includes an NPN-type bipolar junction transistor (BJT).

### Claim 14 (depends on 13)

The modeling circuit of claim 13, wherein the first field effect transistor includes a gate-grounded NMOSFET.

### Claim 15 (depends on 1)

The modeling circuit of claim 1, wherein:
the first field effect transistor includes a p-type metal oxide semiconductor field effect transistor (PMOSFET), and
each of the first and second bipolar transistors includes a PNP-type BJT.

### Claim 16 (depends on 15)

The modeling circuit of claim 15, wherein the first field effect transistor includes a gate-grounded PMOSFET.

### Claim 17

A method of designing an integrated circuit, the method comprising:
obtaining a circuit structure of the integrated circuit, the circuit structure including at least one field effect transistor; and
analyzing the circuit structure and verifying the circuit structure, the analyzing and verifying using a modeling circuit of a field effect transistor,
wherein the modeling circuit includes,
a first field effect transistor on a semiconductor substrate,
a first bipolar transistor having a first collector electrode connected to a first node corresponding to a first electrode of the first field effect transistor, a first emitter electrode connected to a second node corresponding to a second electrode of the first field effect transistor, and a first base electrode,
a second bipolar transistor having a second collector electrode connected to the second node, a second emitter electrode connected to the first node, and a second base electrode connected to the first base electrode of the first bipolar transistor, and
a substrate resistor connected between the first and second base electrodes and a first surface of the semiconductor substrate.

### Claim 18 (depends on 17)

The method of claim 17, wherein the analyzing and the verifying the circuit structure of the integrated circuit includes:
replacing the at least one field effect transistor included in the circuit structure of the integrated circuit with the modeling circuit; and
simulating whether the circuit structure of the integrated circuit including the modeling circuit satisfies a plurality of operating conditions.

### Claim 19 (depends on 17)

The method of claim 17, wherein the integrated circuit includes:
at least one electrostatic discharge (ESD) protection circuit configured to reduce an impact of static electricity; and
at least one functional circuit configured to perform an operation of the integrated circuit,
wherein at least one of the at least one ESD protection circuit includes the at least one field effect transistor, or the at least one functional circuit includes the at least one field effect transistor.

### Claim 20

A modeling circuit of a field effect transistor comprising:
a first n-type metal oxide semiconductor field effect transistor (NMOSFET) having a drain electrode, a source electrode, a gate electrode, and a bulk electrode;
a first resistor connected between the drain electrode of the first NMOSFET and a first node;
a second resistor connected between the source electrode of the first NMOSFET and a second node;
a third resistor connected between the first node and a drain terminal for external connection;
a fourth resistor connected between the second node and a source terminal for external connection;
a first most exquisite transistor model-bipolar junction transistor (MEXTRAM-BJT) having a first collector electrode connected to the first node, a first emitter electrode connected to the second node, and a first base electrode;
a second MEXTRAM-BJT having a second collector electrode connected to the second node, a second emitter electrode connected to the first node, and a second base electrode connected to the bulk electrode of the first NMOSFET and the first base electrode of the first MEXTRAM-BJT;
a substrate resistor connected between the first and second base electrodes and a bulk external connection terminal;
a first diode and a fifth resistor connected in series between the first node and the bulk external connection terminal; and
a second diode and a sixth resistor connected in series between the second node and the bulk external connection terminal,
wherein the first and second resistors correspond to MOSFET active resistances of the first NMOSFET, and
the third and fourth resistors correspond to parasitic BJT active resistances of the first and second MEXTRAM-BJTs.