# US 11,907,627 B2 · Fabricated layout correlation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,627 B2 - Document ID: US11907627B2 - Status: Granted - Kind: B2 - Application number: 17/545,572 - Filed: 2021-12-08 - Published: 2022-06-16 - Granted: 2024-02-20 - Earliest claimed: 2020-12-15 - Assignees: Battelle Memorial Institute - Applicants: Battelle Memorial Institute - Inventors: Adam Kimura; Rohan Prabhu; Noah Mun - Web page: https://patentgrep.com/patent/US11907627B2 ## CPC - G06F 21/75: by inhibiting the analysis of circuitry or operation - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 21/14: against software analysis or reverse engineering, e.g. by obfuscation - G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06N 3/0475: Generative networks - G06N 3/08: Learning methods - G06N 3/09: Supervised learning - G06N 3/094: Adversarial learning - G06F 30/27: using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model - G06F 30/3308: using simulation - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 2119/18: Manufacturability analysis or optimisation for manufacturability - G06T 7/0006: {using a design-rule based approach} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings. ## Claims ### Claim 1 An integrated circuit (IC) assessment device for assessing an IC-under-test, the IC assessment device comprising: an electronic processor; and a non-transitory storage medium storing: a library of as-fabricated standard cell layout renderings constructed using at least one reference layout image acquired of a reference IC; instructions readable and executable by the electronic processor to perform an IC assessment method including identifying instantiated standard cells and their placements in the layout image of the IC-under-test by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as-fabricated standard cell layout renderings; and instructions readable and executable by the electronic processor to perform a method of constructing the library of as-fabricated standard cell layout renderings, the method including: training an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) to transform layout rendering tiles of a layout rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC; and using the trained AI component, transforming standard cell layout renderings of a library of standard cell layout renderings into the as-fabricated standard cell layout renderings forming the library of as-fabricated standard cell layout renderings. ### Claim 2 (depends on 1) The IC assessment device of claim 1 wherein the method of constructing the library of as-fabricated standard cell layout renderings further includes: partitioning the at least one reference layout image into the reference layout image tiles using a tiling scheme; and partitioning a layout rendering of the reference IC into the layout rendering tiles using the same tiling scheme used in the partitioning of the at least one reference layout image whereby each layout rendering tile has a corresponding reference layout image tile. ### Claim 3 (depends on 2) The IC assessment device of claim 2 wherein the method of constructing the library of as-fabricated standard cell layout renderings further includes generating additional layout rendering tiles and corresponding reference layout image tiles used in training the AI component by applying image transforms including at least rotate image transforms and invert image transforms to the layout rendering tiles and their corresponding reference layout image tiles generated by the tiling operations. ### Claim 4 (depends on 1) The IC assessment device of claim 1 wherein the AI component comprises a Conditional Generative Adversarial Network (C-GAN). ### Claim 5 (depends on 1) The IC assessment device of claim 1 wherein: the layout rendering of the reference IC is a GDSII or Open Artwork System Interchange Standard (OASIS) layout rendering of the reference IC, the standard cell layout renderings of the library of standard cell layout renderings are GDSII or OASIS standard cell layout renderings, and the as-fabricated standard cell layout renderings forming the library of as-fabricated standard cell layout renderings are GDSII or OASIS as-fabricated standard cell layout renderings. ### Claim 6 (depends on 5) The IC assessment device of claim 5 wherein the IC assessment method further includes: converting the layout image of the IC-under-test to a GDSII or OASIS layout rendering of the IC-under-test; wherein the identifying of the instantiated standard cells and their placements in the layout image of the IC-under-test includes matching the instantiated standard cells in the GDSII or OASIS layout rendering of the IC-under-test with corresponding GDSII or OASIS as-fabricated standard cell layout renderings retrieved from the library of as-fabricated standard cell layout renderings. ### Claim 7 (depends on 1) The IC assessment device of claim 1 wherein the reference IC is the IC-under-test, and the non-transitory storage medium further stores instructions readable and executable by the electronic processor to generate the layout rendering of the reference IC by operations including: identifying instantiated standard cells and their placements in the at least one reference layout image by matching the instantiated standard cells with corresponding standard cell layout renderings of the library of standard cell layout renderings; and combining the standard cell layout renderings corresponding to the instantiated standard cells in accord with the placements of the instantiated standard cells to generate the layout rendering of the reference IC. ### Claim 8 (depends on 1) The IC assessment device of claim 1 wherein the layout image of the IC-under-test comprises a two-dimensional (2D) layout image acquired by a nondestructive process or a three-dimensional (3D) layout image formed by stacking a plurality of layer images of the IC-under-test acquired by a destructive delayering process. ### Claim 9 (depends on 1) The IC assessment device of claim 1 wherein the IC assessment method further includes: determining connectivity of the instantiated standard cells using the layout image of the IC-under-test or a layout rendering of the IC-under-test generated from the layout image of the IC-under-test; and generating a netlist for the IC-under-test based on the instantiated standard cells and the connectivity. ### Claim 10 (depends on 1) The IC assessment device of claim 1 further comprising: a microscope configured to acquire the layout image of the IC-under-test. ### Claim 11 A non-transitory storage medium storing instructions readable and executable by an electronic processor to perform a method of constructing a library of as-fabricated standard cell layout renderings, the method including: training an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) to transform layout rendering tiles of a layout rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC; and using the trained AI component, transforming standard cell layout renderings of a library of standard cell layout renderings into the as-fabricated standard cell layout renderings forming the library of as-fabricated standard cell layout renderings. ### Claim 12 (depends on 11) The non-transitory storage medium of claim 11 wherein the method of constructing the library of as-fabricated standard cell layout renderings further includes: partitioning the at least one reference layout image into the reference layout image tiles using a tiling scheme; partitioning a layout rendering of the reference IC into the layout rendering tiles using the same tiling scheme used in the partitioning of the at least one reference layout image whereby each layout rendering tile has a corresponding reference layout image tile. ### Claim 13 (depends on 11) The non-transitory storage medium of claim 11 wherein the non-transitory storage medium further stores instructions readable and executable by an electronic processor to perform an IC assessment method including: converting a layout image of the IC-under-test to a layout rendering of the IC-under-test; and identifying instantiated standard cells and their placements in the IC-under-test by matching instantiated standard cells in the layout rendering of the IC-under-test with corresponding as-fabricated standard cell layout renderings retrieved from the library of as-fabricated standard cell layout renderings. ### Claim 14 (depends on 13) The non-transitory storage medium of claim 13 wherein the IC assessment method further includes: determining connectivity of the instantiated standard cells using the layout rendering of the IC-under-test; and generating a netlist for the IC-under-test based on the instantiated standard cells and the connectivity. ### Claim 15 (depends on 13) The non-transitory storage medium of claim 13 wherein: the layout rendering of the reference IC is a GDSII or Open Artwork System Interchange Standard (OASIS) layout rendering of the reference IC, the standard cell layout renderings of the library of standard cell layout renderings are GDSII or OASIS standard cell layout renderings, the as-fabricated standard cell layout renderings forming the library of as-fabricated standard cell layout renderings are GDSII or OASIS as-fabricated standard cell layout renderings, and the layout rendering of the IC-under-test is a GDSII or OASIS layout rendering of the IC-under-test. ### Claim 16 (depends on 13) The non-transitory storage medium of claim 13 wherein the layout image of the IC-under-test comprises one of: (i) a two-dimensional (2D) layout image acquired by a nondestructive process, or (ii) a three-dimensional (3D) layout image formed by stacking a plurality of layer images of the IC-under-test acquired in conjunction with a destructive delayering process. ### Claim 17 An integrated circuit (IC) assessment method for assessing an IC-under-test, the IC assessment method comprising training an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) to transform layout rendering tiles of a GDSII or OASIS rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC; using the trained AI component, transforming GDSII or OASIS standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings into as-fabricated standard cell layout renderings forming a library of as-fabricated standard cell layout renderings; and identifying instantiated standard cells and their placements in the layout image of the IC-under-test by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as-fabricated standard cell layout renderings. ### Claim 18 (depends on 17) The method of claim 17 wherein the identifying further includes: converting the layout image of the IC-under-test to a layout rendering of the IC-under-test; and identifying the instantiated standard cells and their placements in the layout image of the IC-under-test by matching the instantiated standard cells in the converted layout rendering of the IC-under-test with the corresponding as-fabricated standard cell layout renderings retrieved from the library of as-fabricated standard cell layout renderings. ### Claim 19 (depends on 17) The method of claim 17 further comprising: determining connectivity of the instantiated standard cells using the layout image of the IC-under-test or a layout rendering of the IC-under-test generated from the layout image of the IC-under-test; and generating a netlist for the IC-under-test based on the instantiated standard cells and the connectivity.