# US 11,907,580 B2 · Corrective read of a memory device with reduced latency > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,580 B2 - Document ID: US11907580B2 - Status: Granted - Kind: B2 - Application number: 17/645,683 - Filed: 2021-12-22 - Published: 2023-06-22 - Granted: 2024-02-20 - Earliest claimed: 2021-12-22 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Tao Liu; Zhengang Chen; Ting Luo - Web page: https://patentgrep.com/patent/US11907580B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0611: {in relation to response time} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 11/07: Responding to the occurrence of a fault, e.g. fault tolerance - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G06F 2212/7206: Reconfiguration of flash memory system - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration. ## Claims ### Claim 1 An apparatus, comprising: a memory device; and a controller coupled with the memory device and configured to cause the apparatus to: identify a read error based at least in part on receiving, from the memory device, first information that is associated with a first read operation of the memory device; select a trim setting from a plurality of trim settings based at least in part on identifying a data retention condition associated with the first information; transmit, to the memory device, an indication to initiate a second read operation of the memory device in accordance with the selected trim setting; and perform a decoding operation based at least in part on receiving, from the memory device, second information that is associated with the second read operation of the memory device. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receive an indication of a threshold voltage shift associated with a physical address of the memory device for the first read operation; and identify the data retention condition based at least in part on the threshold voltage shift. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein, to select the trim setting, the controller is configured to cause the apparatus to: select between a first trim setting that is associated with a first data retention duration and a second trim setting that is associated with a second data retention duration that is greater than the first data retention duration. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the first trim setting is associated with a first temperature difference between one or more write operations and one or more read operations and the second trim setting is associated with a second temperature difference between one or more write operations and one or more read operations that is less than the first temperature difference. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein transmitting the indication to initiate the second read operation is associated with a selected one of the first trim setting or the second trim setting, and wherein the controller is further configured to cause the apparatus to: transmit, to the memory device based at least in part on the decoding operation being unsuccessful, an indication to initiate a third read operation of the memory device in accordance with the other of the first trim setting or the second trim setting; and perform a second decoding operation based at least in part on receiving, from the memory device, third information that is associated with the third read operation of the memory device. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the controller is further configured to cause the apparatus to: perform a defect management operation based at least in part on the second decoding operation being unsuccessful. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein to perform the decoding operation, the controller is configured to cause the apparatus to perform a hard bit decoding, a soft bit decoding, or any combination thereof. ### Claim 8 A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to: identify a read error based at least in part on receiving, from a memory device, first information that is associated with a first read operation of the memory device; select a trim setting from a plurality of trim settings based at least in part on identifying a data retention condition associated with the first information; transmit, to the memory device, an indication to initiate a second read operation of the memory device in accordance with the selected trim setting; and perform a decoding operation based at least in part on receiving, from the memory device, second information that is associated with the second read operation of the memory device. ### Claim 9 (depends on 8) The non-transitory computer-readable medium of claim 8, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receive an indication of a threshold voltage shift associated with a physical address of the memory device for the first read operation; and identify the data retention condition based at least in part on the threshold voltage shift. ### Claim 10 (depends on 8) The non-transitory computer-readable medium of claim 8, wherein, to select the trim setting, the instructions, when executed by the processor of the electronic device, cause the electronic device to select between a first trim setting that is associated with a first data retention duration and a second trim setting that is associated with a second data retention duration that is greater than the first data retention duration. ### Claim 11 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein the first trim setting is associated with a first temperature difference between one or more write operations and one or more read operations and the second trim setting is associated with a second temperature difference between one or more write operations and one or more read operations that is less than the first temperature difference. ### Claim 12 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein transmitting the indication to initiate the second read operation is associated with a selected one of the first trim setting or the second trim setting, and wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: transmit, to the memory device based at least in part on the decoding operation being unsuccessful, an indication to initiate a third read operation of the memory device in accordance with the other of the first trim setting or the second trim setting; and perform a second decoding operation based at least in part on receiving, from the memory device, third information that is associated with the third read operation of the memory device. ### Claim 13 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform a defect management operation based at least in part on the second decoding operation being unsuccessful. ### Claim 14 (depends on 8) The non-transitory computer-readable medium of claim 8, wherein to perform the decoding operation, the instructions, when executed by the processor of the electronic device, cause the electronic device to perform a hard bit decoding, a soft bit decoding, or any combination thereof. ### Claim 15 A method at a controller, the method comprising: identifying a read error based at least in part on receiving, from a memory device, first information that is associated with a first read operation of the memory device; selecting a trim setting from a plurality of trim settings based at least in part on identifying a data retention condition associated with the first information; transmitting, to the memory device, an indication to initiate a second read operation of the memory device in accordance with the selected trim setting; and performing a decoding operation based at least in part on receiving, from the memory device, second information that is associated with the second read operation of the memory device. ### Claim 16 (depends on 15) The method of claim 15, further comprising: receiving an indication of a threshold voltage shift associated with a physical address of the memory device for the first read operation; and identifying the data retention condition based at least in part on the threshold voltage shift. ### Claim 17 (depends on 15) The method of claim 15, wherein selecting the trim setting comprises: selecting between a first trim setting that is associated with a first data retention duration and a second trim setting that is associated with a second data retention duration that is greater than the first data retention duration. ### Claim 18 (depends on 17) The method of claim 17, wherein the first trim setting is associated with a first temperature difference between one or more write operations and one or more read operations and the second trim setting is associated with a second temperature difference between one or more write operations and one or more read operations that is less than the first temperature difference. ### Claim 19 (depends on 17) The method of claim 17, wherein transmitting the indication to initiate the second read operation is associated with a selected one of the first trim setting or the second trim setting, the method further comprising: transmitting, to the memory device based at least in part on the decoding operation being unsuccessful, an indication to initiate a third read operation of the memory device in accordance with the other of the first trim setting or the second trim setting; and performing a second decoding operation based at least in part on receiving, from the memory device, third information that is associated with the third read operation of the memory device. ### Claim 20 (depends on 19) The method of claim 19, further comprising: performing a defect management operation based at least in part on the second decoding operation being unsuccessful. ### Claim 21 (depends on 15) The method of claim 15, wherein performing the decoding operation comprises performing a hard bit decoding, a soft bit decoding, or any combination thereof.