# US 11,907,579 B2 · Memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,579 B2 - Document ID: US11907579B2 - Status: Granted - Kind: B2 - Application number: 17/590,322 - Filed: 2022-02-01 - Published: 2023-03-23 - Granted: 2024-02-20 - Earliest claimed: 2021-09-21 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hidekazu Nanzawa - Web page: https://patentgrep.com/patent/US11907579B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/061: {Improving I/O performance} - G06F 3/0613: {in relation to throughput} - G06F 3/0634: {by changing the state or mode of one or more devices} - G06F 3/064: {Management of blocks} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 3/068: {Hybrid storage device} - G06F 11/3466: {Performance evaluation by tracing or monitoring} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0882: Page mode - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 29/023: {in clock generator or timing circuitry} - G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing - G06F 2212/1004: Compatibility, e.g. with legacy hardware - G06F 2212/1016: Performance improvement - G06F 2212/1044: Space efficiency improvement - G06F 2212/7202: Allocation control and policies - G06F 2212/7204: Capacity control, e.g. partitioning, end-of-life degradation - G06F 2212/7206: Reconfiguration of flash memory system - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 29/56012: {Timing aspects, clock generation, synchronisation} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a memory cell array having pages. The memory system is configured to execute a first operation method and a second operation method. The memory system includes a control information storage unit in which a first value is set for pages having a write operation speed that is slower than a first speed, and a second value is set for pages having a write operation speed that is equal to or higher than the first speed. The memory system is configured to, at the time of write operation, select the first operation method for a target page having the first value and perform the write operation using the first operation method, and select the second operation method for a target page having the second value and perform the write operation using the second operation method. ## Claims ### Claim 1 A memory system comprising: a non-volatile memory; and a memory controller, wherein the non-volatile memory includes a memory cell array having first and second pages each including a plurality of storage elements, and the memory system is configured to execute one of at least a first operation method for storing n-bit (n is a natural number) data per storage element and a second operation method for storing m-bit (m is a natural number satisfying m>n) data per storage element, and includes a control information storage unit in which a first value is set for the first page having a pre-determined write operation speed that is slower than a first speed, and a second value is set for the second page having a pre-determined write operation speed that is equal to or higher than the first speed, and the memory system is configured to, at the time of a write operation, select one of the at least first and second operation methods for writing to a page in accordance with a value set in the control information storage unit for the page and perform the write operation using the selected operation method, wherein the first operation method is selected for the first page having the first value set in the control information storage unit and the write operation is performed on the first page using the first operation method, and the second operation method is selected for the second page having the second value set in the control information storage unit and the write operation is performed on the second page using the second operation method, wherein the pre-determined write operation speed for each of the first and second pages is determined during a test of measuring a performance index of the memory system executed near the time of a shipment of the memory system or at the time of designing the memory system, and a difference between a write operation speed during execution of the write operation in the first page using the first operation method and a write operation speed during execution of the write operation in the second page using the second operation method is smaller than a difference between the pre-determined write operation speed of the first page and the pre-determined write operation speed of the second page. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the memory system is further configured to: at the time of a read operation, select a first read method for the first page having the first value set in the control information storage unit and perform the read operation using the first read method, and select a second read method for the second page having the second value set in the control information storage unit and perform the read operation using the second read method. ### Claim 3 (depends on 1) The memory system according to claim 1, wherein the memory cell array further has a third page including a plurality of storage elements, and the memory system is further configured to: execute one of at least the first operation method, the second operation method, and a third operation method for storing I-bit (I is a natural number satisfying m>n>I) data in the storage elements, and at the time of the write operation, select the third operation method for the third page having a pre-determined write operation speed that is slower than a second speed, which is slower than the first speed, and perform the write operation using the third operation method. ### Claim 4 (depends on 3) The memory system according to claim 3, wherein the memory system is further configured to: at the time of a read operation, select a third read method for the third page having the pre-determined write operation speed that is slower than the second speed and perform the read operation using the third read method. ### Claim 5 (depends on 3) The memory system according to claim 3, wherein a difference between a write operation speed in the third page using the third operation method and the write operation speed in the second page using the second operation method is smaller than a difference between the pre-determined write operation speed of the third page and the pre-determined write operation speed of the second page. ### Claim 6 (depends on 1) The memory system according to claim 1, wherein the memory system is configured to read from and write to the memory cell array in units of pages, and to perform an erase operation on the memory cell array in units of blocks, each block containing a plurality of pages. ### Claim 7 A method of operating a memory system, the memory system including a non-volatile memory including a memory cell array having a plurality of blocks, each block having a plurality of pages including a first page and a second page, each of the pages including a plurality of storage elements, and a control information storage unit in which a first value is set for the first page having a pre-determined write operation speed that is slower than a first speed, and a second value is set for the second page having a pre-determined write operation speed that is equal to or higher than the first speed, said method comprising: selecting one of at least a first operation method and a second operation method for writing to a page in accordance with a value set in the control information storage unit for the page and performing a write operation using the selected operation method, wherein n-bit (n is a natural number) data is stored per storage element when the first operation method is used and m-bit (m is a natural number satisfying m>n) data is stored per storage element when the second operation method is used, wherein the first page having the first value set in the control information storage unit is written to using the first operation method, and the second page having the second value set in the control information storage unit is written to using the second operation method, wherein the pre-determined write operation speed for each of the first and second pages is determined during a test of measuring a performance index of the memory system executed near the time of a shipment of the memory system or at the time of designing the memory system, and a difference between a write operation speed during execution of the write operation in the first page using the first operation method and a write operation speed during execution of the write operation in the second page using the second operation method is smaller than a difference between the pre-determined write operation speed of the first page and the pre-determined write operation speed of the second page. ### Claim 8 (depends on 7) The method according to claim 7, further comprising: reading from the first page having the first value set in the control information storage unit using a first read method; and reading from the second page having the second value set in the control information storage unit using a second read method. ### Claim 9 (depends on 7) The method according to claim 7, wherein the plurality of pages of each block further includes a third page, said method further comprising: writing to the third page having a pre-determined write operation speed that is slower than a second speed, which is slower than the first speed, using a third operation method for storing I-bit (I is a natural number satisfying m>n>I) data in each of the plurality of storage elements. ### Claim 10 (depends on 9) The method according to claim 9, further comprising: reading from the third page having the pre-determined write operation speed that is slower than the second speed using a third read method. ### Claim 11 (depends on 9) The method according to claim 9, wherein a difference between a write operation speed in the third page using the third operation method and the write operation speed in the second page using the second operation method is smaller than a difference between the pre-determined write operation speed of the third page and the pre-determined write operation speed of the second page. ### Claim 12 (depends on 7) The method according to claim 7, wherein a read operation and a write operation on the memory cell array are performed in units of pages, and an erase operation on the memory cell array is performed in units of blocks. ### Claim 13 A method of configuring a memory system that comprises a non-volatile memory including a memory cell array having a plurality of blocks, each block having a plurality of pages including a first page and a second page, each of the pages including a plurality of storage elements, said method comprising: setting a first value in a control information storage unit for the first page having a pre-determined write operation speed that is slower than a first speed; and setting a second value in the control information storage unit for the second page having a pre-determined write operation speed that is equal to or higher than the first speed, wherein during a write operation, one of at least a first operation method and a second operation method is selected for writing to a page in accordance with a value set in the control information storage unit for the page and the write operation is performed using the selected operation method, wherein n-bit (n is a natural number) data is stored per storage element when the first operation method is used and m-bit (m is a natural number satisfying m>n) data is stored per storage element when the second operation method is used, wherein the first page having the first value set in the control information storage unit is written to using the first operation method, and the second page having the second value set in the control information storage unit is written to using the second operation method, and wherein the pre-determined write operation speed for each of the first and second pages is determined during a test of measuring a performance index of the memory system executed near the time of a shipment of the memory system or at the time of designing the memory system, and a difference between a write operation speed during execution of the write operation in the first page using the first operation method and a write operation speed during execution of the write operation in the second page using the second operation method is smaller than a difference between the pre-determined write operation speed of the first page and the pre-determined write operation speed of the second page. ### Claim 14 (depends on 13) The method according to claim 13, wherein during a read operation, the first page having the first value set in the control information storage unit is read using a first read method, and the second page having the second value set in the control information storage unit is read using a second read method. ### Claim 15 (depends on 13) The method according to claim 13, wherein the plurality of pages of each block further includes a third page, and during the write operation, the third page having a pre-determined write operation speed that is slower than a second speed, which is slower than the first speed, is written using a third operation method for storing I-bit (I is a natural number satisfying m>n>I) data in each of the plurality of storage elements. ### Claim 16 (depends on 15) The method according to claim 15, wherein during a read operation, the third page having the pre-determined write operation speed that is slower than the second speed is read using a third read method. ### Claim 17 (depends on 15) The method according to claim 15, wherein a difference between a write operation speed in the third page using the third operation method and the write operation speed in the second page using the second operation method is smaller than a difference between the pre-determined write operation speed of the third page and the pre-determined write operation speed of the second page. ### Claim 18 (depends on 13) The method according to claim 13, wherein a read operation and a write operation on the memory cell array are performed in units of pages, and an erase operation on the memory cell array is performed in units of blocks.