# US 11,907,574 B2 · Memory devices for suspend and resume operations

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- Number: US 11,907,574 B2
- Document ID: US11907574B2
- Status: Granted
- Kind: B2
- Application number: 17/382,615
- Filed: 2021-07-22
- Published: 2022-06-30
- Granted: 2024-02-20
- Earliest claimed: 2020-12-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Umberto Siciliani; Floriano Montemurro
- Web page: https://patentgrep.com/patent/US11907574B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.

## Claims

### Claim 1

A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
receive a command to perform a program operation;
in response to the command to perform the program operation, begin execution of the program operation;
in response to executing the program operation, pull down a ready/busy control signal to indicate the memory device is busy executing the program operation;
while executing the program operation, receive a command to perform a read operation with the ready/busy control signal pulled down;
in response to the command to perform the read operation, suspend the execution of the program operation while keeping the ready/busy control signal pulled down; and
with the execution of the program operation suspended and with the ready/busy control signal pulled down, execute the read operation while keeping the ready/busy control signal pulled down.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the controller is further configured to suspend the execution of the program operation without receiving a suspend command.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the controller is further configured to:
in response to the command to perform the read operation, accept the command to perform the read operation and continue the execution of the program operation until an execution breakpoint is reached; and
in response to reaching the execution breakpoint, suspend the execution of the program operation.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the controller is further configured to:
while executing the program operation, receive a plurality of commands to perform a respective plurality of read operations; and
with the execution of the program operation suspended, execute the plurality of read operations.

### Claim 5 (depends on 4)

The memory device of claim 4, further comprising:
a command register to latch the plurality of commands to perform the respective plurality of read operations in the order they are received,
wherein the controller is further configured to execute the plurality of read operations in the order they were received.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the controller is further configured to:
in response to the execution of the read operation completing, resume the execution of the program operation without receiving a resume command.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the controller is further configured to:
in response to the execution of the read operation completing, resume the execution of the program operation in response to receiving a resume command.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the command to perform the read operation comprises one of a read parameter page command, a read unique identifier (ID) command, a set feature command, a get feature command, a read page multi-plane command, and an intermediate word line (iWL) read command.

### Claim 9

A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
receive a command to perform an erase operation;
in response to the command to perform the erase operation, begin execution of the erase operation;
in response to executing the erase operation, pull down a ready/busy control signal to indicate the memory device is busy executing the erase operation;
while executing the erase operation, receive a command to perform a read operation with the ready/busy control signal pulled down;
in response to the command to perform the read operation, suspend the execution of the erase operation while keeping the ready/busy control signal pulled down; and
with the execution of the erase operation suspended and with the ready/busy control signal pulled down, execute the read operation while keeping the ready/busy control signal pulled down.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the controller is further configured to suspend the execution of the erase operation without receiving a suspend command.

### Claim 11 (depends on 9)

The memory device of claim 9, wherein the controller is further configured to:
in response to the command to perform the read operation, accept the command to perform the read operation and continue the execution of the erase operation until an execution breakpoint is reached; and
in response to reaching the execution breakpoint, suspend the execution of the erase operation.

### Claim 12 (depends on 9)

The memory device of claim 9, wherein the controller is further configured to:
while executing the erase operation, receive a plurality of commands to perform a respective plurality of read operations; and
with the execution of the erase operation suspended, execute the plurality of read operations.

### Claim 13 (depends on 12)

The memory device of claim 12, further comprising:
a command register to latch the plurality of commands to perform the respective plurality of read operations in the order they are received,
wherein the controller is further configured to execute the plurality of read operations in the order they were received.

### Claim 14 (depends on 9)

The memory device of claim 9, wherein the controller is further configured to:
in response to the execution of the read operation completing, resume the execution of the erase operation without receiving a resume command.

### Claim 15 (depends on 9)

The memory device of claim 9, wherein the controller is further configured to:
in response to the execution of the read operation completing, resume the execution of the erase operation in response to receiving a resume command.

### Claim 16 (depends on 9)

The memory device of claim 9, wherein the command to perform the read operation comprises one of a read parameter page command, a read unique identifier (ID) command, a set feature command, a get feature command, a read page multi-plane command, an intermediate word line (iWL) read command, a cache read command, and a copyback command.

### Claim 17

A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
receive a command to perform a program operation;
in response to the command to perform the program operation, begin execution of the program operation;
receive a command to suspend the execution of the program operation;
in response to the command to suspend the execution of the program operation, suspend the execution of the program operation;
with the execution of the program operation suspended, receive a command to perform a read operation;
in response to the command to perform the read operation, execute the read operation;
in response to executing the read operation, pull down a ready/busy control signal to indicate the memory device is busy executing the read operation; and
in response to the execution of the read operation completing and with the ready/busy control signal pulled down, resume the execution of the program operation while keeping the ready/busy control signal pulled down.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the controller is further configured to resume the execution of the program operation without receiving a resume command.

### Claim 19 (depends on 17)

The memory device of claim 17, wherein the controller is further configured to:
in response to the command to suspend the execution of the program operation, continue the execution of the program operation until an execution breakpoint is reached; and
in response to reaching the execution breakpoint, suspend the execution of the program operation.

### Claim 20 (depends on 17)

The memory device of claim 17, wherein the controller is further configured to:
with the execution of the program operation suspended, receive a plurality of commands to perform a respective plurality of read operations; and
in response to the plurality of commands to perform the respective plurality of read operations, execute the plurality of read operations.

### Claim 21 (depends on 20)

The memory device of claim 20, further comprising:
a command register to latch the plurality of commands to perform the respective plurality of read operations in the order they are received,
wherein the controller is further configured to execute the plurality of read operations in the order they were received.

### Claim 22 (depends on 17)

The memory device of claim 17, wherein the controller is further configured to:
in response to executing the program operation, pull down the ready/busy control signal to indicate the memory device is busy executing the program operation;
with the ready/busy control signal pulled down, receive the command to suspend the execution of the program operation;
in response to suspending the execution of the program operation, release the ready/busy control signal to indicate the memory device is ready; and
with the ready/busy control signal released, receive the command to perform the read operation.

### Claim 23 (depends on 17)

The memory device of claim 17, wherein the command to perform the read operation comprises one of a read parameter page command, a read unique identifier (ID) command, a set feature command, a get feature command, a read page multi-plane command, and an intermediate word line (iWL) read command.

### Claim 24

A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
receive a command to perform an erase operation;
in response to the command to perform the erase operation, begin execution of the erase operation;
receive a command to suspend the execution of the erase operation;
in response to the command to suspend the execution of the erase operation, suspend the execution of the erase operation;
with the execution of the erase operation suspended, receive a command to perform a read operation;
in response to the command to perform the read operation, execute the read operation;
in response to executing the read operation, pull down a ready/busy control signal to indicate the memory device is busy executing the read operation; and
in response to the execution of the read operation completing and with the ready/busy control signal pulled down, resume the execution of the erase operation while keeping the ready/busy control signal pulled down.

### Claim 25 (depends on 24)

The memory device of claim 24, wherein the controller is further configured to resume the execution of the erase operation without receiving a resume command.

### Claim 26 (depends on 24)

The memory device of claim 24, wherein the controller is further configured to:
in response to the command to suspend the execution of the erase operation, continue the execution of the erase operation until an execution breakpoint is reached; and
in response to reaching the execution breakpoint, suspend the execution of the erase operation.

### Claim 27 (depends on 24)

The memory device of claim 24, wherein the controller is further configured to:
with the execution of the erase operation suspended, receive a plurality of commands to perform a respective plurality of read operations; and
in response to the plurality of commands to perform the respective plurality of read operations, execute the plurality of read operations.

### Claim 28 (depends on 27)

The memory device of claim 27, further comprising:
a command register to latch the plurality of commands to perform the respective plurality of read operations in the order they are received,
wherein the controller is further configured to execute the plurality of read operations in the order they were received.

### Claim 29 (depends on 24)

The memory device of claim 24, wherein the controller is further configured to:
in response to executing the erase operation, pull down the ready/busy control signal to indicate the memory device is busy executing the erase operation;
with the ready/busy control signal pulled down, receive the command to suspend the execution of the erase operation;
in response to suspending the execution of the erase operation, release the ready/busy control signal to indicate the memory device is ready; and
with the ready/busy control signal released, receive the command to perform the read operation.

### Claim 30 (depends on 24)

The memory device of claim 24, wherein the command to perform the read operation comprises one of a read parameter page command, a read unique identifier (ID) command, a set feature command, a get feature command, a read page multi-plane command, an intermediate word line (iWL) read command, a cache read command, and a copyback command.